The thermal resistance model of a thyristor converter valve considering its water-cooling circuit is estab-lished by combining the mechanism of a thyristor connected in series with the water-cooling circuit, which can calculate the water temperature at the inlet of each heat sink, as well as the junction temperature of each thyristor accordingly. This model is used to calculate the thermal resistance of each component in the converter valve in an example, and a steady-state thermal resistance model is built to calculate the junction temperature of the thyristor. Calculation results show that the maximum calculation error of thyristor junction temperature can reach 10.81% when considering the differ-ence of coolant temperature in the water-cooling circuit.

As electronic devices continue to miniaturize and integrate, thermal simulation has become a critical factor during the design phase. The conventional finite element method(FEM) used for the thermal simulation of electronics packaging modules faces a trade-off between computational efficiency and accuracy, and it also encounters difficulties in handling problems of large deformation and grid distortion, which will cause errors in the results. In this paper, a thermal simulation system for electronics packaging modules based on the smoothed particle hydrodynamics (SPH) algorithm is proposed. The SPH algorithm is based on the meshless Lagrange numerical method, and it resolves the heat conduction equation by discretizing the simulation object into a set of particles, thus accurately predicting the heat conduction and heat dissipation in electronics packaging modules. Since it does not need to generate a large number of micro-meshes, there is no grid distortion. Compared with FEM, the SPH algorithm achieves an accuracy error between 1% and 2%, thereby improving the simulation efficiency by approximately 30 times. Therefore, this algorithm is highly suitable in simulating the thermal behavior of a dynamical system with a complex structure.

A rapid solution method for the thyristor electro-thermal coupling model based on the conjugate gradient method is developed to address the limitations of traditional solution techniques in terms of processing efficiency and computational cost. By optimizing the iteration process and convergence criteria, the solution efficiency and accuracy are significantly improved. A novel parameter selection strategy is introduced to automatically adjust the algorithm's iteration step size, thus accelerating the convergence speed and reducing the computational resource consumption. Compared with the traditional solution methods, the optimization approach achieves an average reduction of 10% in solution time and an 8% increase in solution accuracy. This progress demonstrates the effectiveness of the adaptive conjugate gradient method in the rapid solution of electro-thermal coupling models, providing an efficient and reliable computational tool for the thermal management of power electronic devices. The proposed method exhibits significant efficiency improvement and good accuracy under various test conditions, offering an innovative solution for efficiently solving the thyristor electro-thermal coupling models. This method is also of practical significance for related research in the field of power electronics.

As the service environment of power semiconductor devices becomes more and more severe, the third-generation semiconductor represented by silicon carbide (SiC) has become the mainstream of industry applications owing to its excellent high-temperature performance. However, the lack of bounding materials which not only match with SiC chips but also have a low cost and a high melting point has become a bottleneck in the development of the industry. Cu-Sn intermetallic compounds (IMCs) are considered to be ideal bounding materials for SiC chips because of their low cost, good conductivity and characteristics that meet the requirements of low-temperature bonding and high-temperature service. Aimed at the power semiconductor device packaging, the preparation and reliability of Cu-Sn full IMC joints at home and abroad in recent years are analyzed and reviewed, and the problems to be solved at present and the development trend in the future are discussed.

Enhancing the power density of vehicle-grade power modules is of significance for the performance of electric vehicles. The two-dimensional layout used in conventional power modules results in large parasitic inductance, which limits the switching speed and bus voltage and further affects the increase in power density. To solve this problem, an IGBT power module with EconoDUAL packaging was taken as the research object, and a three-dimensional layout was designed using the stacked DBC method to develop a 1 200 V/1 200 A IGBT power module. The layout structure of the proposed power module was introduced in detail. Compared with those obtained using the conventional two-dimensional layout methods, the parasitic inductance decreased by 58%. Additionally, electrical performance tests including a double-pulse test with pulse current of 1 200 A under bus voltage of 800 V were conducted on the power module, thereby verifying the improved power density of the module. To maintain the heat dissipation performance while increasing the power density,

Owing to their advantages in switching speed, temperature characteristics and voltage withstand capability, silicon carbide (SiC) power modules are gradually applied in the motor controllers of electric vehicles. As a core component of electric vehicles, the motor controller demands high electro-thermal characteristics of power modules, posing a significant challenge to SiC packaging. In this paper, the mainstream HybridPACK Drive module packaging is taken as an example, the driver and direct bonded copper(DBC) layout are optimized, and the copper wire bonding technology is introduced to balance the module's electro-thermal performance and reliability. In addition, the response surface methodology is used to optimize the elliptical Pin-Fin heat sink, thereby enhancing the module's heat dissipation performance. Finally, prototypes of SiC power modules before and after optimization were fabricated for comparison, and a double-pulse test setup and a power back-to-back test setup were established respectively to evaluate the electro-thermal performance of the two approaches. Experimental results indicate that when the chip spacing was equal to half the die width, the optimized power module can achieve a superior thermal performance while maintaining the electrical characteristics.

The bidirectional switch is extensively applied in the fields such as state-solid breakers and photovoltaic inverters, and increasing attention is paid to the bidirectional switch of SiC power modules owing to its low power loss and high switching frequency. However, due to the traditional packaging methods for Si power modules, the bidirectional switch of the SiC power module is challenged by the issue of high switching speed. Aimed at the low-inductance packaging requirement, a chip-on-chip 3D packaging method is proposed for the bidirectional switch of the SiC power module. The circuit topology and geometric structure of the 3D packaging are given, and the communication loop and parasitic inductance of the 3D packaging are analyzed. In addition, the process was designed for the 3D packaging, and a prototype of the bidirectional switch of the SiC power module was fabricated. Experimental results of a double-pulse test verified the feasibility and effectiveness of the proposed 3D packaging for the bidirectional switch of the SiC power module.

Silicon carbide (SiC) devices possess advantages such as high voltage resistance, low losses and high thermal conductivity, making them of significant importance for the development of the electric vehicle industry. A design for a SiC MOSFET power module utilizing large-chip packaging was proposed, and experiments were conducted to analyze the module's electrical performance. Simulations were set up to compare the module temperature under two conditions, i.e., electrical characteristics only and a combination of electrical characteristics and temperature feedback. Simulation results indicate that under identical operating conditions, the SiC MOSFET power module designed with large-chip packaging exhibited stronger conduction current capability, smaller temperature variations and improved electrical performance.

Silicon carbide(SiC) MOSFETs are widely used in high-voltage, high-frequency and high-power-density applications for new energy electric vehicles owing to their superior material properties. During the process of double-sided cooling, the effect of chip layout spacing on heat dissipation and chip temperature uniformity was usually ignored, and the effect of chip temperature uniformity on the parallel current uniformity of multiple chips was not taken into account. A double-sided cooling package structure was designed, the effect on chip temperature uniformity due to chip layout spacing was analyzed, and the influences of different junction temperatures and different chip layouts on parasitic parameters and switching characteristics were also discussed. Aimed at different chip layout spacings and different cooling conditions, the effectiveness of the proposed method was verified through a large number of simulations and the response face analysis and comparison, providing technical method guidance and quantitative analysis for the influences of SiC power module packaging on chip temperature uniformity and switching characteristics.

With the improvement of the integration degree of power modules, the optimization of their heat transfer structures has become a focus in the development. The topology optimization(TO) can maximize the cooling performance by transforming the morphology and structure of heat sinks, thus receiving extensive attention. However, in the TO process, the temperature distribution of modules and heat sinks needs to be calculated in each iteration step, consuming a large amount of computing resource and calculation time. To accelerate the TO process of traditional heat sinks, a fast iterative method combining neural network (NN) synchronous learning and the traditional solid isotropic material with penalization (SIMP)-based TO methods is put forward. First, an NN prediction model based on the encoder-decoder structure is constructed, which can iteratively evolve the shape of heat sinks to achieve a fast prediction of optimized structures. Second, the NN model is integrated into the TO process of the heat sink based on the SIMP method, and the NN is trained synchronously using the intermediate morphology obtained in the iteration process. Finally, aimed at the single-chip and dual-chip modules, the results obtained by the new method and traditional iterative methods are compared to validate the accuracy and rapidity of the proposed NN synchronous leaning method.