With the continuous advancement of radar technology, broadband phased array radar has been widely applied in fields such as remote sensing, environmental monitoring, and 5G base station communications due to its high resolution, multi-tasking capability, and adaptability to complex electromagnetic environments. However, traditional phased array radars rely on phase shifters to control beam direction, which can lead to beam squint in broadband applications, ultimately reducing detection accuracy. To address this issue, this paper presents a high-area-efficiency true time delay (TTD) circuit based on an artificial transmission line(ATL) delay unit. Fabricated using a 0.13 μm SiGe BiCMOS process, the TTD circuit operates across the frequency range from S to Ku bands and features a 6-bit digital delay control, achieving a minimum delay resolution of 6 ps and a maximum delay of 378 ps. The circuit incorporates delay reference paths with T-type and π-type attenuator structures, ensuring optimal gain matching with the delay units. Additionally, by integrating passive switches and distributed cascaded gain equalizers, the design enhances delay accuracy and gain flatness. Through HFSS optimization of spacing of inductors in the ATL delay unit, the layout efficiently reduces inductor area consumption. As a result, the fabricated chip measures only 3 mm × 0.9 mm, offering a delay density of 141.6 ps per unit area. Measurement results show that the root mean square (RMS) delay error across all states is less than 5.9 ps, while the circuit exhibits a gain performance of -5.5 to -1 dB within its operating frequency range under a 2.5V power supply. This work makes a significant contribution to the development of high-performance phased array radar systems.

In response to the high reliability requirements of missile-borne equipment in complex mechanical environments, a design method for vibration isolators based on high-manganese copper alloy is proposed. Firstly, a dynamic model of the missile-borne equipment was established, and the damping characteristics of the high-manganese copper alloy were thoroughly analyzed to determine its damping parameters. Subsequently, to balance the damping and strength properties of the vibration isolator, an optimization design model for the missile-borne equipment vibration isolator based on high-manganese copper alloy was constructed. The genetic algorithm was employed to optimize the relevant design parameters of the vibration isolator, resulting in an improved design scheme. Finite element analysis and mechanical testing demonstrates that, compared to traditional silicone rubber vibration isolators, the deformation of the high-manganese copper alloy-based vibration isolator was reduced by 40%, while its damping characteristics still met the vibration isolation requirements of the missile-borne equipment. This fully proves the superiority and rationality of the proposed design scheme.

Digital channelization has been widely applied in the field of electronic reconnaissance. The multi-phase structure of digital channelization can reduce data rates, making it easier to implement in FPGA. However, when the number of sub-channels is large, the data rate of each sub-channel will be significantly lower than the processing rate of FPGA, resulting in a waste of FPGA resources. In this paper, we introduce two-dimensional DFT into traditional DFT digital channelization structure and propose a channelization structure that matches the processing rate of FPGA, namely the digital channelization structure based on two-dimensional DFT. This structure is verified through simulation in Matlab(Matrix Laboratory)，and its computational complexity is analyzed and compared with that of traditional DFT-based digital channelization structure. Subsequently, the FPGA implementation block diagram and FPGA resource utilization are presented, and then the structure is tested on a hardware platform. The results show that the digital channelization structure based on two-dimensional DFT can correctly perform channelization of various signals. Compared with the traditional DFT-based digital channelization structure, it reduces computational complexity and significantly improves the efficiency of FPGA resources utilization, facilitating the FPGA implementation of large-scale digital channelization, which has certain engineering significance.

By optimizing the reference impedance of the T-junction power divider and reducing the impedance mutation, the working bandwidth is significantly broadened. A one-to-four T-junction broadband power divider with a center frequency of 15 GHz is designed. Its structure is mainly composed of T-junctions and microstrip transmission lines, with a size of 25×3.8 mm². The simulation results show that, without increasing the network size and complexity, compared with the traditional four-way power divider, the working bandwidth defined by the 20 dB return loss is broadened to 3.44 octaves (6.5 ~ 24 GHz). Within the working frequency band, the insertion loss is less than 6.7 dB (including the theoretical 6 dB loss of one-to-four division). A prototype is fabricated and tested, and the measured results are in good agreement with the simulation results. This power divider features a “narrow and long”structure, making it suitable for use in broadband one-dimensional array antennas such as those in mobile communication base stations and radars, and it has a promising application prospect.

Ocean internal wave is a common and significant ocean phenomenon that occurs between different density layers in the ocean. In this study, 92 Sentinel-1 images containing internal solitary waves, collected from 2015 to 2019, were used. Through preprocessing and visual interpretation, label data were generated to form a high-quality dataset containing 4 608 pairs of sample images. To address the inadequacy in the research of multi-scale internal solitary wave feature extraction, this paper proposes a multiscale internal solitary wave feature extraction model based on the Swin-Unet network to improve the extraction capability for internal solitary waves at different scales. The performance evaluation results show that, compared to the U-Net method, the proposed Swin-Unet model improved by 2.3% in F1 score, 2.44% in precision, and 12.12% in mean intersection over union (mIoU). The internal solitary wave extraction results at different scales in the Andaman Sea were subsequently analyzed, and the improved model was applied to Sentinel-1 full-track SAR imagery, verifying its applicability and robustness in complex marine regions. Experimental results demonstrate that the proposed model, based on the constructed dataset, can automatically extract ocean internal solitary wave features from SAR images.

To meet the requirements for miniaturization, broadbandization, integration, and Electro Magnetic Compatibility(EMC) in radar and communication systems，the ceramic nesting technology was used to design and fabricate a low-loss X-band Surface Mount Technology (SMT) microstrip circulator based on Mg ferrite materials. Through three-dimensional full electromagnetic simulation, a microstrip gyro-magnetic junction with comb structure was designed to achieve device miniaturization and broadbandization. To realize SMT packaging, a ceramic-filled metallized via structure was optimally designed using HFSS, and the St12 metal with high permeability was used as a shielding cover to ensure that the circulator can work independently without interference from other components in the system, achieving electromagnetic shielding and magnetic conduction. Finally, the device was fabricated and tested according to the optimal design results. The test results demonstrated that the designed SMT circulator had a full package size of 6 mm×6 mm×4 mm, with a bandwidth of 60%, Loss<0.8 dB, Isolation>18 dB, and VSWR<1.30. The resulting circulator shows no electromagnetic interference with the outside world, and is suitable for large-scale automatic mounting.

Integrated circuit nanotechnology is gradually approaching the physical limit. Therefore, relying on heterogeneous integration technology to continue and expand Moore Law is becoming increasingly important. The vertical interconnection of signals from various integrated chips is achieved through technologies such as through silicon via (TSV) or through glass via (TGV), while high-density interconnection in the horizontal direction can be achieved through rewiring layer (RDL) technology. The article summarizes the comparison between TGV technology and adapter boards, elaborates on the current application status in the field of passive systems and RF 3D integration, analyzes the TGV process capability and the current technical progress of domestic and foreign manufacturers, and explores the existing technical difficulties and future development trends of the TGV.

This paper delves into the applications and the technological advancements of silicon-based analog beam- forming chips in high-frequency, high-bandwidth communication and phased-array radar systems. The context of 5G and the prospective 6G networks, which impose increasingly stringent demands on data transmission rates, anti-interference capabilities, and signal quality, So beam-forming technology has emerged as a pivotal factor in enhancing the performance of both communication and radar systems. Initially, this paper expounds on the fundamental principles of silicon-based analog beam-forming chips, highlighting their distinctive advantages in terms of low power consumption, high integration, and precise beam control. Moreover, it explores in depth exploration of the strategies for optimizing the silicon-based material processing techniques to improve frequency response and bandwidth handling capabilities. Subsequently, the paper elaborates on the key technologies embodied in silicon-based analog beamforming chips, including attenuators and phase shifters. Conclusively, the paper offers a forward-looking perspective on the future development trends of silicon-based analog beam-forming chips. Particular emphasis is placed on discussing the potential of technologies such as adaptive beam-forming, low-latency control, multi-functional integration, and the application of novel materials. The novelty of this research lies in the introduction of beam isolation technology, and the proposition of a viable approach to enhance frequency response and bandwidth processing capabilities through the optimization of silicon-based processes. This contributes to providing essential technical support for future wireless communication and radar systems.

With the development of measurement and control technology, the Ka-band has become an important direction for the development of next-generation satellite communications and millimeter-wave radar. Low-noise amplifiers are core components at the front end of receivers, and their noise temperature directly affects key system indicators such as the receiving sensitivity and action distance of the system. This paper introduces an ultra-low-noise temperature amplifier working in the Ka-band, achieving ultra-wideband, ultra-low noise temperature, miniaturization and generalization. The measured results show that within the frequency range of 26.5～40 GHz, the gain is more than 35 dB, the noise temperature is less than 215 K, and the VSWR is less than 2.38 with the size of 32 mm×19 mm×8 mm.

This paper presents the design of a 24~30 GHz frequency tripler based on a 65 nm CMOS process, aiming at enhancing the performance of local oscillator (LO) chains in millimeter-wave communication systems. By leveraging the nonlinear characteristics of MOS transistors, the design optimizes the bias voltage and matches network to enhance the third harmonic while suppressing the fundamental and higher-order harmonics. The proposed frequency tripler employs a two-stage architecture: the first stage utilizes a differential common-source common-gate (CSCG) structure, efficiently extracts and amplifies the third harmonic, while the second stage, a power amplifier, further optimizes the bandwidth and output power through load-pull analysis. Post-layout simulation results demonstrate a 3 dB bandwidth of 24~30 GHz, achieving a relative bandwidth of 22%. At 27 GHz, the tripler delivers a saturated output power of 7.4 dBm, with a maximum in-band conversion gain of 4.2 dB. The suppression levels for the fundamental and fifth harmonics are 29 dBc and 28 dBc, respectively, maintaining good performance over a wide input power range. This design provides an efficient and compact solution for K/Ka-band LO chains in millimeter-wave communication systems.