Owing to its obvious advantages such as high control flexibility, no commutation failure and strong dy-namic reactive power support capability, the voltage sourced converter based high-voltage direct-current (VSC-HVDC) transmission technology has been widely applied in scenarios including point-to-point transmission, back-to-back inter-connections and DC grids. As a core piece of equipment in VSC-HVDC transmission engineering, the VSC valve achieves AC/DC energy conversion through frequent switching of power electronic devices. In this paper, the key design requirements for VSC valves in different application scenarios are systematically summarized by combining with practical experiences accumulated in engineering, the commonly used power devices and VSC valve topologies in VSC-HVDC transmission engineering are compared and analyzed, and their development trends are projected. In addition, different schemes for two typical application scenarios in the future are also compared, providing reference for the applications of VSC-HVDC transmission technology in high-voltage, large-capacity and long-distance transmission scenarios.

The advancements in research on automotive power device packaging have significantly improved the dynamic performance and driving range of electric vehicles, making them more efficient and reliable. With the continuous optimization of automotive power device packaging, the electric vehicle industry is expected to embrace a broader market prospect and development space. In recent years, power device packaging modeling, packaging structure and optimization, thermal management and junction temperature monitoring, gate drive and applications, reliability analysis, and online monitoring have become current research hotspots and have received sustained attention from both the academic and industrial sectors. To promote discussions on the challenges and hot issues related to automotive power devices packaging and their applications, a special issue titled "High Reliability Power Device Packaging and Assistant Technology in EV Application" has been launched in the Journal of Power Supply.

Accurately obtaining the electromagnetic characteristics of high-voltage and high-power switching devices is crucial for predicting the electromagnetic interference in a system in which the devices are located. Research is focused on an equivalent method of switch waveforms for analyzing the electromagnetic characteristics of high-voltage and high-power switching devices. Aimed at the problem that the existing equivalent waveforms are too ideal to reflect the complex spectral components in the switching transients of devices, an analytical model for the electromagnetic characteristics of devices considering their switching processes is proposed. Starting from the time-domain analytical formula for the analytical model and based on the Fourier transform theory, the frequency-domain analytical formula for the analytical model is derived, and the spectral envelope characteristic parameters are analyzed to obtain the spectral characteristics of the analytical model. The theoretical analysis was verified by using the measured switching waveforms of Si IGBT and SiC MOSFET devices.

With the widespread applications of insulated gate bipolar transistors (IGBTs) in power electronic systems, the accurate acquisition of junction temperature which affects their reliability has become crucial. However, one of the main forms of module failure is the aging of the solder layer, which can have a significant impact on the junction temperature. To accurately estimate the junction temperature, the advantages of two traditional thermal network models (i.e., Cauer and Foster) are combined in this paper, and an interface method for the two models is studied, so that the combination is completed. The aging of the chip solder layer is taken into account, and a hybrid thermal network model is proposed. Finally, through the comparison of finite element simulation and experimental test with the calculation results of the hybrid thermal network model, it is verified that the hybrid thermal network model can achieve an accurate junction temperature estimation, providing a basis for monitoring the operating status of the module.

The thermal resistance model of a thyristor converter valve considering its water-cooling circuit is estab-lished by combining the mechanism of a thyristor connected in series with the water-cooling circuit, which can calculate the water temperature at the inlet of each heat sink, as well as the junction temperature of each thyristor accordingly. This model is used to calculate the thermal resistance of each component in the converter valve in an example, and a steady-state thermal resistance model is built to calculate the junction temperature of the thyristor. Calculation results show that the maximum calculation error of thyristor junction temperature can reach 10.81% when considering the differ-ence of coolant temperature in the water-cooling circuit.

As electronic devices continue to miniaturize and integrate, thermal simulation has become a critical factor during the design phase. The conventional finite element method(FEM) used for the thermal simulation of electronics packaging modules faces a trade-off between computational efficiency and accuracy, and it also encounters difficulties in handling problems of large deformation and grid distortion, which will cause errors in the results. In this paper, a thermal simulation system for electronics packaging modules based on the smoothed particle hydrodynamics (SPH) algorithm is proposed. The SPH algorithm is based on the meshless Lagrange numerical method, and it resolves the heat conduction equation by discretizing the simulation object into a set of particles, thus accurately predicting the heat conduction and heat dissipation in electronics packaging modules. Since it does not need to generate a large number of micro-meshes, there is no grid distortion. Compared with FEM, the SPH algorithm achieves an accuracy error between 1% and 2%, thereby improving the simulation efficiency by approximately 30 times. Therefore, this algorithm is highly suitable in simulating the thermal behavior of a dynamical system with a complex structure.

A rapid solution method for the thyristor electro-thermal coupling model based on the conjugate gradient method is developed to address the limitations of traditional solution techniques in terms of processing efficiency and computational cost. By optimizing the iteration process and convergence criteria, the solution efficiency and accuracy are significantly improved. A novel parameter selection strategy is introduced to automatically adjust the algorithm's iteration step size, thus accelerating the convergence speed and reducing the computational resource consumption. Compared with the traditional solution methods, the optimization approach achieves an average reduction of 10% in solution time and an 8% increase in solution accuracy. This progress demonstrates the effectiveness of the adaptive conjugate gradient method in the rapid solution of electro-thermal coupling models, providing an efficient and reliable computational tool for the thermal management of power electronic devices. The proposed method exhibits significant efficiency improvement and good accuracy under various test conditions, offering an innovative solution for efficiently solving the thyristor electro-thermal coupling models. This method is also of practical significance for related research in the field of power electronics.

As the service environment of power semiconductor devices becomes more and more severe, the third-generation semiconductor represented by silicon carbide (SiC) has become the mainstream of industry applications owing to its excellent high-temperature performance. However, the lack of bounding materials which not only match with SiC chips but also have a low cost and a high melting point has become a bottleneck in the development of the industry. Cu-Sn intermetallic compounds (IMCs) are considered to be ideal bounding materials for SiC chips because of their low cost, good conductivity and characteristics that meet the requirements of low-temperature bonding and high-temperature service. Aimed at the power semiconductor device packaging, the preparation and reliability of Cu-Sn full IMC joints at home and abroad in recent years are analyzed and reviewed, and the problems to be solved at present and the development trend in the future are discussed.

Enhancing the power density of vehicle-grade power modules is of significance for the performance of electric vehicles. The two-dimensional layout used in conventional power modules results in large parasitic inductance, which limits the switching speed and bus voltage and further affects the increase in power density. To solve this problem, an IGBT power module with EconoDUAL packaging was taken as the research object, and a three-dimensional layout was designed using the stacked DBC method to develop a 1 200 V/1 200 A IGBT power module. The layout structure of the proposed power module was introduced in detail. Compared with those obtained using the conventional two-dimensional layout methods, the parasitic inductance decreased by 58%. Additionally, electrical performance tests including a double-pulse test with pulse current of 1 200 A under bus voltage of 800 V were conducted on the power module, thereby verifying the improved power density of the module. To maintain the heat dissipation performance while increasing the power density,

Owing to their advantages in switching speed, temperature characteristics and voltage withstand capability, silicon carbide (SiC) power modules are gradually applied in the motor controllers of electric vehicles. As a core component of electric vehicles, the motor controller demands high electro-thermal characteristics of power modules, posing a significant challenge to SiC packaging. In this paper, the mainstream HybridPACK Drive module packaging is taken as an example, the driver and direct bonded copper(DBC) layout are optimized, and the copper wire bonding technology is introduced to balance the module's electro-thermal performance and reliability. In addition, the response surface methodology is used to optimize the elliptical Pin-Fin heat sink, thereby enhancing the module's heat dissipation performance. Finally, prototypes of SiC power modules before and after optimization were fabricated for comparison, and a double-pulse test setup and a power back-to-back test setup were established respectively to evaluate the electro-thermal performance of the two approaches. Experimental results indicate that when the chip spacing was equal to half the die width, the optimized power module can achieve a superior thermal performance while maintaining the electrical characteristics.

The bidirectional switch is extensively applied in the fields such as state-solid breakers and photovoltaic inverters, and increasing attention is paid to the bidirectional switch of SiC power modules owing to its low power loss and high switching frequency. However, due to the traditional packaging methods for Si power modules, the bidirectional switch of the SiC power module is challenged by the issue of high switching speed. Aimed at the low-inductance packaging requirement, a chip-on-chip 3D packaging method is proposed for the bidirectional switch of the SiC power module. The circuit topology and geometric structure of the 3D packaging are given, and the communication loop and parasitic inductance of the 3D packaging are analyzed. In addition, the process was designed for the 3D packaging, and a prototype of the bidirectional switch of the SiC power module was fabricated. Experimental results of a double-pulse test verified the feasibility and effectiveness of the proposed 3D packaging for the bidirectional switch of the SiC power module.

Silicon carbide (SiC) devices possess advantages such as high voltage resistance, low losses and high thermal conductivity, making them of significant importance for the development of the electric vehicle industry. A design for a SiC MOSFET power module utilizing large-chip packaging was proposed, and experiments were conducted to analyze the module's electrical performance. Simulations were set up to compare the module temperature under two conditions, i.e., electrical characteristics only and a combination of electrical characteristics and temperature feedback. Simulation results indicate that under identical operating conditions, the SiC MOSFET power module designed with large-chip packaging exhibited stronger conduction current capability, smaller temperature variations and improved electrical performance.

Silicon carbide(SiC) MOSFETs are widely used in high-voltage, high-frequency and high-power-density applications for new energy electric vehicles owing to their superior material properties. During the process of double-sided cooling, the effect of chip layout spacing on heat dissipation and chip temperature uniformity was usually ignored, and the effect of chip temperature uniformity on the parallel current uniformity of multiple chips was not taken into account. A double-sided cooling package structure was designed, the effect on chip temperature uniformity due to chip layout spacing was analyzed, and the influences of different junction temperatures and different chip layouts on parasitic parameters and switching characteristics were also discussed. Aimed at different chip layout spacings and different cooling conditions, the effectiveness of the proposed method was verified through a large number of simulations and the response face analysis and comparison, providing technical method guidance and quantitative analysis for the influences of SiC power module packaging on chip temperature uniformity and switching characteristics.

With the improvement of the integration degree of power modules, the optimization of their heat transfer structures has become a focus in the development. The topology optimization(TO) can maximize the cooling performance by transforming the morphology and structure of heat sinks, thus receiving extensive attention. However, in the TO process, the temperature distribution of modules and heat sinks needs to be calculated in each iteration step, consuming a large amount of computing resource and calculation time. To accelerate the TO process of traditional heat sinks, a fast iterative method combining neural network (NN) synchronous learning and the traditional solid isotropic material with penalization (SIMP)-based TO methods is put forward. First, an NN prediction model based on the encoder-decoder structure is constructed, which can iteratively evolve the shape of heat sinks to achieve a fast prediction of optimized structures. Second, the NN model is integrated into the TO process of the heat sink based on the SIMP method, and the NN is trained synchronously using the intermediate morphology obtained in the iteration process. Finally, aimed at the single-chip and dual-chip modules, the results obtained by the new method and traditional iterative methods are compared to validate the accuracy and rapidity of the proposed NN synchronous leaning method.

Power semiconductor devices are the core of electric energy conversion and electric drive based on the power electronics technology, which have broad application prospects in new energy generation, transportation, aerospace and other fields. However, the problems such as degradation, failure and reliability caused by heat generation have become bottlenecks that limit their further development, and it is urgent to explore effective thermal management methods to improve their reliability and service life. In this paper, based on the introduction of thermal management methods for power modules, the research progress in active thermal management methods is reviewed in detail, and these methods are divided into device-level, system-level and multi-parameter comprehensive methods according to the difference in control parameters. In addition, various methods are analyzed and compared. Finally, the development trend and prospect of technologies for power devices which are related to junction temperature are put forward, providing a reference for the subsequent research and applications.

Press-pack insulated gate bipolar transistor (PP-IGBT) modules are widely used in high-power applications such as flexible DC converter valves owing to their superior electrical performance and reliability. Therefore, an accurate observation of the junction temperature of a IGBT chip is important for monitoring its operating status and evaluating its remaining lifetime. The existing junction temperature observation methods are mostly designed for bonded-lead IGBTs, which cannot be applied directly because the characteristics of PP modules are not taken into account. Aimed at the PP IGBTs in large-capacity converter valves, a practical method for calibrating the on-state voltage drop and junction temperature of modules is proposed, and the online estimation error of junction temperature is comprehensively analyzed. Then, a junction temperature calibration scheme is designed based on a 5SNA 3000K452300 PP IGBT module(4 500 V, 3 000 A) produced by ABB, including experimental circuits, temperature calibration range selection, junction temperature control method, measurement circuits and calibration experimental procedure. Finally, based on a pulse test platform, the proposed method was verified. Experimental results show that the junction temperature calibration and observation scheme proposed was effective, the junction temperature observation error was within ±5 °C, and it can be applied to the case of differences in PP IGBT modules.

As a novel and extensively applied switching device, silicon carbide metal-oxide-semiconductor field-ef fect transistor(SiC MOSFET) offers a faster switching speed and lower device loss in practical applications, thereby en-hancing the converter efficiency and delivering a superior performance. Aimed at the driving characteristics of SiC MOS-FET, the influence of parasitic parameters on its performance was analyzed. To investigate the relationship between the gate-source voltage and turn-on time of SiC MOSFET, a two-pulse experimental platform was also established. However, there are certain drawbacks with the existing domestic SiC MOSFET. Based on the experimental platform and other power products, the changes in conduction time, driving loss and negative voltage amplitude after replacing the imported SiC MOSFET with domestic devices were analyzed.

Owing to its advantages including lower switching stress, harmonic components and a better anti-interference capability, the diode neutral point clamped (NPC) three-level inverter has become a prominent topology for DC-AC converters used in new energy fields such as photovoltaic and energy storage. The NPC three-level insulated gate bipolar transistor(IGBT) power semiconductor module which is widely used in high-power applications is studied. The commutation circuit in the NPC three-level power module is analyzed, and a precise simulation and evaluation method for the corresponding parasitic parameters is given. According to the principle of minimizing the parasitic parameters of the commutation circuit, a dynamic characteristic test circuit suitable for the NPC three-level power semiconductor module is designed. Based on the commutation circuit and the operating principle of circuit, a drive circuit for the NPC three-level power module is designed, and a driving scheme that enhances drive current, prevents shoot-through and allows for adjustable dead time is formulated. Finally, through dynamic testing of the NPC three-level IGBT module, a comprehensive assessment of the dynamic loss in power devices under various operating conditions is conducted.

AC-DC Buck-type power factor correction (PFC) converters are widely applied in low-voltage scenarios. However, they typically suffer from low power factor(PF) and high total harmonic distortions of input current(THDi) caused by the input current dead zones. To solve this problem, firstly, a high PF Buck-type bridgeless PFC converter with hybrid operation modes is proposed by introducing a Buck-Boost converter cell, which operates in the Buck and Buck-Boost modes in the positive and negative half-line cycles, respectively. Although the Buck-Boost cell's efficiency is inferior to that of the Buck cell, the proposed converter can operate in the Buck-Boost mode in the negative half-line cycle, thereby minimizing the dead zones to improve PF and reduce THDi. The proposed converter operates in the Buck mode in the positive half-line cycle, inheriting the high efficiency of the Buck cell. Secondly, the operation modes and PF of the proposed bridgeless converter are analyzed to show its high PF feature. Finally, simulations and experimental tests were conducted to verify the feasibility and theoretical analysis of the proposed converter, and a comparison of performance between the proposed and conventional Buck-type PFC converters was also performed.

LLC resonant converters are widely applied in on-board power supplies owing to their high power density, high efficiency and small size, and their reliability is critical to the driving safety and passenger experiences. However, the complicated working conditions and harsh environment under which vehicles operate have become a huge challenge to power devices. When a switch failure occurs, the resonant converter cannot maintain a stable output voltage while operating at a resonant point, and both efficiency and output capability of the system will decrease substantially. To make the converter more compatible with fault occasions, an improved LLC topology and its control strategy are proposed in this paper, which can ensure that the output voltage remains unaffected when a switch failure occurs and the converter operates near the resonant frequency. Additionally, an optimized Burst control strategy is designed to suppress the overvoltage of the resonant capacitor during the fault tolerance transition and guarantee a smooth fault tolerance process. Finally, simulation and experimental results verified the effectiveness of the proposed method.

In the burgeoning field of new energy vehicles, silicon carbide representing a new generation of semi-conductor power devices is progressively replacing silicon-based IGBTs, which also sets higher standards for the motor control performance within the corresponding innovative technological ecosystem. The precision of motor parameters is becoming increasingly critical for enhancing the performance of electric control systems as they evolve from the tradi-tional PI control and direct torque control to advanced algorithms such as model predictive control and neural network control. Aimed at the problem that the classic linear model for permanent magnet synchronous motors cannot adapt to complex and variable conditions due to nonlinear factors such as cross-saturation, a nonlinear magnetic flux identifica-tion method based on Gaussian process regression is proposed. By employing a second-order generalized integrator to acquire the magnetic flux data under dynamic conditions, the system identification is completed. Finally, the effective-ness of the proposed approach and the accuracy of parameter identification were verified through simulation and experi-mental results.

The application of wide bandgap semiconductor devices makes the motor drive system of electric vehicles (EVs) more compact and lightweight, but it also causes more serious electromagnetic interference (EMI), which makes the reliability of the drive system face severe challenges. To solve this problem, a 24 V/2 A EMI DC filter is taken as an example, and through the analysis of noise source, filter principle and impedance influence, the filter parameters are designed according to the index of insertion loss. At the same time, considering the starting impact at the starting time of the whole vehicle, a soft starting circuit is added to further improve the reliability of the EV drive system. Experimental results verified the EMI suppression effect and the soft starting function of the filter, proving the feasibility and effectiveness of the filter design.

In the development of technologies for power electronic devices used in automobiles, the power modules are developing towards the direction of miniaturization and high power density. As a result, the high-frequency switching of power devices used in automobiles will increase the fatigue failure risk of bonding wires. To improve the strength and reliability of bonding, the action mechanism of bonding parameters at different stages was revealed from the perspective of the bonding principle at first, and the optimization intervals for different parameters were obtained using single-factor experiments. Subsequently, a systematic investigation of the influence of wire bonding materials on bonding reliability was conducted through numerical simulations and aging tests. Results indicate that compared with Al bonding wires, Cu bonding wires exhibited higher maximum temperatures and higher maximum equivalent stress. However, due to material properties, Cu bonding wires only achieved half the maximum plastic strain of Al bonding wires. Based on power cycling tests, the lifetime of Cu bonding wires was approximately four times that of Al bonding wires. Moreover, Cu bonding wires exhibited a higher degree of variability in bonding quality, with the phenomenon of stepwise signal escalation due to the detachment of a single wire serving as an early warning signal for potential failures in daily operations.

Press-pack IGBT power devices are the core component in the new power system application equipment, and health management can improve their service lifetime and operational reliability, thus guaranteeing the safety and stability of new power systems. First, the package structure and main failure modes of press-pack IGBT devices are introduced. Second, the existing health condition monitoring methods are classified and analyzed according to different types of characteristic parameters. Third, the principles and characteristics of the existing lifetime prediction methods for press-pack IGBTs are summarized. Finally, a comprehensive comparative analysis of the existing health management technologies is performed, and the problems in the health management methods for press-pack IGBTs which need to be further studied and the development trends in the future are pointed out.

To study the degradation mechanism of silicon carbide metal-oxide-semiconductor field effect transistors (SiC MOSFETs) under dynamic drain-source stress, a dynamic reverse bias test platform with an adjustable dVds/dt capability up to 80 V/ns was developed. A dynamic high-temperature reverse bias test of commercial SiC MOSFET was carried out, and the effect of dynamic drain-source stress with a high voltage change rate on the electrical characteristics of SiC MOSFET was discussed. Experimental results show that the threshold voltage and forward conduction voltage of the bulk diode increased, indicating that the gate oxygen layer and the bulk diode above the JFET region of the device may be degraded. Sentaurus TCAD was used to analyze the weak position of plane-gate SiC MOSFET under high drain-source voltage and a high voltage change rate, and hole traps were set at the gate oxygen layer junction and the body diode region to simulate the effect of dynamic high-temperature reverse bias on the dynamic and static parameters of SiC MOSFET.

With the applications of an ultra-wideband pulse signal system in many important fields such as the intelligent sensing technology for new energy automobile, the research and development of high-amplitude and fast-front pulse sources has been widely studied. To meet the demand of an ultrafast power semiconductor switch in nanosecond front pulses, the terminal failure mechanism of avalanche bipolar junction transistor in voltage ramp triggering mode is studied in this paper. The static characteristics of a simulation model are compared with those of a sample device, and the dynamic switching characteristics of the sample device were tested. On the basis of a successful device with a nanosecond switching speed, its failure phenomenon in voltage ramp triggering mode was analyzed.

Press-pack IGBT power devices are one of the core components in new power system application equipment. Due to the complex working environment and variable working conditions of power equipment, the fatigue failure of power devices will be caused over time. To ensure the safe and stable operation of key equipment in power systems, it is necessary to assess the remaining lifetime of press-pack IGBT devices, thereby timely taking appropriate actions before a device failure occurs. First, a multi-physics field model of press-pack IGBT devices is established, and the mechanical parameters affecting their aging process are analyzed. Based on the analysis results, a suitable model for press-pack IGBTs is selected from the existing lifetime prediction models, and a lifetime assessment software applicable to press-pack IGBTs is developed. Finally, a case study is conducted based on the developed lifetime assessment software, and the assessment result of devices is obtained, providing guidance for the applications of devices.

In a direct current(DC) power transmission system, the stable operation of a valve base electronics(VBE) device is crucial for its safety. However, the traditional methods for detecting the component failures in VBE device circuit boards rely on time-consuming manual inspections or rule-based automation systems, which are often inefficient and limited in the detection accuracy. To address this problem, a method for identifying the component failure areas in VBE boards is proposed in this paper, which uses an enhanced SqueezeNet deep learning model. By incorporating depth-wise separable convolutions and residual connections, the enhanced SqueezeNet model aims to improve the accuracy of component failure detection while reducing the demand for computational resources. Experiments on a VBE board component failure dataset demonstrate that the proposed method outperforms the traditional methods and the standard SqueezeNet model in terms of detection accuracy and computational efficiency, and it achieves an accuracy rate of 95.27%, which is 4.45% higher than that of the standard model. The results of this research not only enhance the efficiency and accuracy of component failure detection in VBE boards, but also provide a novel technical reference for the diagnosis of component failures in similar equipment in power systems.

Gate oxide degradation is a key reliability issue that limits the widespread applications of silicon carbide metal-oxide-semiconductor field-effect transistors(SiC MOSFETs), and online monitoring is an important means to improve the reliability of SiC MOSFETs as it can obtain the gate-oxide health status in real time. In this paper, an online monitoring method for SiC MOSFET gate-oxide health status based on gate reference voltage is proposed. The basic principle of using the gate reference voltage to monitor the gate-oxide health status is introduced in detail, and a gate reference voltage online extraction circuit is also put forward. The designed extraction circuit was verified by pulse tests, indicating that it can achieve online extraction. In addition, aging tests were conducted, and results verified that the proposed method can effectively monitor the gate oxide health status. The designed circuit can be integrated into gate driver without significantly increasing the system complexity.

Compared with that in a Si device, the area of near interface oxide traps in a SiC MOSFET is wider, and the corresponding density of traps is two orders of magnitude higher. A lot of traps which are continuously capturing or releasing charges will cause the threshold voltage (Vt) to fluctuate with time, leading to the difficulty in accurately and repeatedly measuring the value of Vith. In the standard method, the value of Vith is measured using a preprocessing method to ensure the consistence in measuring the trap charge state in each time. However, the preprocessed trap state which is affected by drain-source voltages is not taken into account in the standard method, which will bring errors to the Vth test. Aimed at this problem, the transfer curves under the influences of different drain-source voltage pulses were measured at first, which show the effects of different drain-source voltages on Vth. Second, the influence of drain-source voltage on the trap charge state was analyzed based on the transient current method, thus clarifying the mechanism of the influence of drain-source voltage on traps. Finally, the influences of different drain-source voltages on Vith measurement were com-pared. Results indicate that the drain-source voltage affects the positive and negative electric field between the gate and drain, thereby affecting the trap charge state and causing the Vith drift. It is suggested that a smaller drain-source voltage should be used when measuring Vith to improve the measurement accuracy and reduce errors caused by testing factors in reliability experiments.

The accurate and reliable switching current information is important for power electronic converters to realize closed-loop control, harmonic suppression and short-circuit protection, which is conducive to further improving the reliability of power devices. The PCB Rogowski coil current sensor has an important research value and application prospect owing to its advantages of high bandwidth, small size, low cost and low intrusion. However, its measurement accuracy is seriously limited by the drift error and droop error in the traditional integral processing circuit. A resettable integrator is used to avoid the continuous accumulation of drift error while eliminating the influence of droop error. At the same time, a digital compensation strategy for the drift error and offset error in the resettable integrator is proposed, which uses a digital signal processor to control the digital-to-analog conversion module to generate an analog compensation signal and eliminates errors by means of a high-speed subtractor. As a result, this method has advantages of a high compensation accuracy and simple adjustment, and it can greatly reduce the influence due to integral errors. Finally, double-pulse, multiple-pulse and short-circuit protection experiments were carried out based on a double-pulse test platform, and the performance of the proposed PCB Rogowski coil current sensor was verified.

With the rapid development of ultra high voltage direct current(DC) power transmission technology, the stability of valve base electronics (VBE) device is crucial for ensuring the reliability and efficiency of DC power transmission. The defects in VBE device circuit boards, such as short circuits and failed components, directly affect the system stability. However, the existing detection methods including manual microscopic inspection and automatic detection algorithms are often limited by their low efficiency and insufficient accuracy. In this paper, an automatic visual inspection method based on point pattern matching is proposed to address these challenges. This method significantly improves its detection accuracy and efficiency by generating point patterns that represent key areas and further matching them, which is particularly suitable for rapid quality control on production lines. Experimental validation shows that the proposed method significantly outperforms the traditional methods in terms of detection speed and accuracy, providing an effective technical solution for improving the quality of DC power transmission equipment and demonstrating important practical value.

At present, multi-level three-phase voltage source inverters are widely applied in high-voltage and high-power electronic equipment. To solve the problem of DC-side capacitor voltage imbalance during the operation of the traditional three-phase voltage source inverter, the inverter structure is optimized in this paper based on the space vector modulation switch DC power supply. The equivalent model of a multi-level three-phase voltage source inverter is established, the space vector modulation algorithm of the 60° coordinate is used to realize the space vector modulation, and the capacitor voltage balance algorithm is used to fully take into account the switching sequence between different vectors, thus realizing the capacitor current balance. Experimental results show that compared with the traditional method, the proposed method can modulate the multi-level three-phase voltage source inverter, the output line voltage waveform distortion rate is 0.18%, and the voltage fluctuation at the capacitor point can be controlled within 3 V, indicating that this method is superior to the comparison method and has a better application performance.

Aimed at the problem that the control modes of interconnecting power converters (IPCs) are complicated to assign and difficult to control when different types of power grids are connected, a novel grid-forming(GFM) control method for IPCs that interconnect high voltage direct current (HVDC) and high voltage alternating current (HVAC) sub-grids is proposed. This method uses modular multilevel converters (MMCs) to control AC and DC terminals simultaneously. In addition, two dual-port GFM MMC control strategies are put forward. Finally, a simulation comparison between single-port GFM control and the proposed two-port GFM control is performed. Results show that compared with the single-port GFM control, the two-port GFM control method is more flexible to emergencies(i.e., line and generator outage), and there is no need to choose the control mode of GFM or grid-following(GFL) for IPC ports in the power grid.

The power control mechanism of cascaded island microgrids (MGs) composed of dispatchable and non-dis-patchable distributed generations (DGs) is complex, and the voltage and frequency regulation is difficult. Aimed at these problems, a novel decentralized master-slave power distribution control method is proposed in this paper to realize the voltage and frequency regulation and power distribution of the cascaded island MGs including second-class DGs. The control methods for master and slave DGs are designed, respectively. The master DG is responsible for adjusting the fre-quency and voltage of MG. Meanwhile, the slave DGs in MPPT mode can run under certain bus voltage, which can max-imally use the output power from non-dispatchable DGs and perform automatic power reduction under the light load condition, thereby effectively guaranteeing the safety and stability of the system. Finally, the effectiveness of the pro-posed method is verified by simulation and experimental results.