The application of wide bandgap semiconductor devices makes the motor drive system of electric vehicles (EVs) more compact and lightweight, but it also causes more serious electromagnetic interference (EMI), which makes the reliability of the drive system face severe challenges. To solve this problem, a 24 V/2 A EMI DC filter is taken as an example, and through the analysis of noise source, filter principle and impedance influence, the filter parameters are designed according to the index of insertion loss. At the same time, considering the starting impact at the starting time of the whole vehicle, a soft starting circuit is added to further improve the reliability of the EV drive system. Experimental results verified the EMI suppression effect and the soft starting function of the filter, proving the feasibility and effectiveness of the filter design.

With the applications of an ultra-wideband pulse signal system in many important fields such as the intelligent sensing technology for new energy automobile, the research and development of high-amplitude and fast-front pulse sources has been widely studied. To meet the demand of an ultrafast power semiconductor switch in nanosecond front pulses, the terminal failure mechanism of avalanche bipolar junction transistor in voltage ramp triggering mode is studied in this paper. The static characteristics of a simulation model are compared with those of a sample device, and the dynamic switching characteristics of the sample device were tested. On the basis of a successful device with a nanosecond switching speed, its failure phenomenon in voltage ramp triggering mode was analyzed.

In a direct current(DC) power transmission system, the stable operation of a valve base electronics(VBE) device is crucial for its safety. However, the traditional methods for detecting the component failures in VBE device circuit boards rely on time-consuming manual inspections or rule-based automation systems, which are often inefficient and limited in the detection accuracy. To address this problem, a method for identifying the component failure areas in VBE boards is proposed in this paper, which uses an enhanced SqueezeNet deep learning model. By incorporating depth-wise separable convolutions and residual connections, the enhanced SqueezeNet model aims to improve the accuracy of component failure detection while reducing the demand for computational resources. Experiments on a VBE board component failure dataset demonstrate that the proposed method outperforms the traditional methods and the standard SqueezeNet model in terms of detection accuracy and computational efficiency, and it achieves an accuracy rate of 95.27%, which is 4.45% higher than that of the standard model. The results of this research not only enhance the efficiency and accuracy of component failure detection in VBE boards, but also provide a novel technical reference for the diagnosis of component failures in similar equipment in power systems.

Gate oxide degradation is a key reliability issue that limits the widespread applications of silicon carbide metal-oxide-semiconductor field-effect transistors(SiC MOSFETs), and online monitoring is an important means to improve the reliability of SiC MOSFETs as it can obtain the gate-oxide health status in real time. In this paper, an online monitoring method for SiC MOSFET gate-oxide health status based on gate reference voltage is proposed. The basic principle of using the gate reference voltage to monitor the gate-oxide health status is introduced in detail, and a gate reference voltage online extraction circuit is also put forward. The designed extraction circuit was verified by pulse tests, indicating that it can achieve online extraction. In addition, aging tests were conducted, and results verified that the proposed method can effectively monitor the gate oxide health status. The designed circuit can be integrated into gate driver without significantly increasing the system complexity.

Press-pack IGBT power devices are one of the core components in new power system application equipment. Due to the complex working environment and variable working conditions of power equipment, the fatigue failure of power devices will be caused over time. To ensure the safe and stable operation of key equipment in power systems, it is necessary to assess the remaining lifetime of press-pack IGBT devices, thereby timely taking appropriate actions before a device failure occurs. First, a multi-physics field model of press-pack IGBT devices is established, and the mechanical parameters affecting their aging process are analyzed. Based on the analysis results, a suitable model for press-pack IGBTs is selected from the existing lifetime prediction models, and a lifetime assessment software applicable to press-pack IGBTs is developed. Finally, a case study is conducted based on the developed lifetime assessment software, and the assessment result of devices is obtained, providing guidance for the applications of devices.

Compared with that in a Si device, the area of near interface oxide traps in a SiC MOSFET is wider, and the corresponding density of traps is two orders of magnitude higher. A lot of traps which are continuously capturing or releasing charges will cause the threshold voltage (Vt) to fluctuate with time, leading to the difficulty in accurately and repeatedly measuring the value of Vith. In the standard method, the value of Vith is measured using a preprocessing method to ensure the consistence in measuring the trap charge state in each time. However, the preprocessed trap state which is affected by drain-source voltages is not taken into account in the standard method, which will bring errors to the Vth test. Aimed at this problem, the transfer curves under the influences of different drain-source voltage pulses were measured at first, which show the effects of different drain-source voltages on Vth. Second, the influence of drain-source voltage on the trap charge state was analyzed based on the transient current method, thus clarifying the mechanism of the influence of drain-source voltage on traps. Finally, the influences of different drain-source voltages on Vith measurement were com-pared. Results indicate that the drain-source voltage affects the positive and negative electric field between the gate and drain, thereby affecting the trap charge state and causing the Vith drift. It is suggested that a smaller drain-source voltage should be used when measuring Vith to improve the measurement accuracy and reduce errors caused by testing factors in reliability experiments.

With the rapid development of ultra high voltage direct current(DC) power transmission technology, the stability of valve base electronics (VBE) device is crucial for ensuring the reliability and efficiency of DC power transmission. The defects in VBE device circuit boards, such as short circuits and failed components, directly affect the system stability. However, the existing detection methods including manual microscopic inspection and automatic detection algorithms are often limited by their low efficiency and insufficient accuracy. In this paper, an automatic visual inspection method based on point pattern matching is proposed to address these challenges. This method significantly improves its detection accuracy and efficiency by generating point patterns that represent key areas and further matching them, which is particularly suitable for rapid quality control on production lines. Experimental validation shows that the proposed method significantly outperforms the traditional methods in terms of detection speed and accuracy, providing an effective technical solution for improving the quality of DC power transmission equipment and demonstrating important practical value.

The power control mechanism of cascaded island microgrids (MGs) composed of dispatchable and non-dis-patchable distributed generations (DGs) is complex, and the voltage and frequency regulation is difficult. Aimed at these problems, a novel decentralized master-slave power distribution control method is proposed in this paper to realize the voltage and frequency regulation and power distribution of the cascaded island MGs including second-class DGs. The control methods for master and slave DGs are designed, respectively. The master DG is responsible for adjusting the fre-quency and voltage of MG. Meanwhile, the slave DGs in MPPT mode can run under certain bus voltage, which can max-imally use the output power from non-dispatchable DGs and perform automatic power reduction under the light load condition, thereby effectively guaranteeing the safety and stability of the system. Finally, the effectiveness of the pro-posed method is verified by simulation and experimental results.

At present, multi-level three-phase voltage source inverters are widely applied in high-voltage and high-power electronic equipment. To solve the problem of DC-side capacitor voltage imbalance during the operation of the traditional three-phase voltage source inverter, the inverter structure is optimized in this paper based on the space vector modulation switch DC power supply. The equivalent model of a multi-level three-phase voltage source inverter is established, the space vector modulation algorithm of the 60° coordinate is used to realize the space vector modulation, and the capacitor voltage balance algorithm is used to fully take into account the switching sequence between different vectors, thus realizing the capacitor current balance. Experimental results show that compared with the traditional method, the proposed method can modulate the multi-level three-phase voltage source inverter, the output line voltage waveform distortion rate is 0.18%, and the voltage fluctuation at the capacitor point can be controlled within 3 V, indicating that this method is superior to the comparison method and has a better application performance.

With the widespread applications of insulated gate bipolar transistors (IGBTs) in power electronic systems, the accurate acquisition of junction temperature which affects their reliability has become crucial. However, one of the main forms of module failure is the aging of the solder layer, which can have a significant impact on the junction temperature. To accurately estimate the junction temperature, the advantages of two traditional thermal network models (i.e., Cauer and Foster) are combined in this paper, and an interface method for the two models is studied, so that the combination is completed. The aging of the chip solder layer is taken into account, and a hybrid thermal network model is proposed. Finally, through the comparison of finite element simulation and experimental test with the calculation results of the hybrid thermal network model, it is verified that the hybrid thermal network model can achieve an accurate junction temperature estimation, providing a basis for monitoring the operating status of the module.