As the service environment of power semiconductor devices becomes more and more severe, the third-generation semiconductor represented by silicon carbide (SiC) has become the mainstream of industry applications owing to its excellent high-temperature performance. However, the lack of bounding materials which not only match with SiC chips but also have a low cost and a high melting point has become a bottleneck in the development of the industry. Cu-Sn intermetallic compounds (IMCs) are considered to be ideal bounding materials for SiC chips because of their low cost, good conductivity and characteristics that meet the requirements of low-temperature bonding and high-temperature service. Aimed at the power semiconductor device packaging, the preparation and reliability of Cu-Sn full IMC joints at home and abroad in recent years are analyzed and reviewed, and the problems to be solved at present and the development trend in the future are discussed.

With the improvement of the integration degree of power modules, the optimization of their heat transfer structures has become a focus in the development. The topology optimization(TO) can maximize the cooling performance by transforming the morphology and structure of heat sinks, thus receiving extensive attention. However, in the TO process, the temperature distribution of modules and heat sinks needs to be calculated in each iteration step, consuming a large amount of computing resource and calculation time. To accelerate the TO process of traditional heat sinks, a fast iterative method combining neural network (NN) synchronous learning and the traditional solid isotropic material with penalization (SIMP)-based TO methods is put forward. First, an NN prediction model based on the encoder-decoder structure is constructed, which can iteratively evolve the shape of heat sinks to achieve a fast prediction of optimized structures. Second, the NN model is integrated into the TO process of the heat sink based on the SIMP method, and the NN is trained synchronously using the intermediate morphology obtained in the iteration process. Finally, aimed at the single-chip and dual-chip modules, the results obtained by the new method and traditional iterative methods are compared to validate the accuracy and rapidity of the proposed NN synchronous leaning method.

Owing to its obvious advantages such as high control flexibility, no commutation failure and strong dy-namic reactive power support capability, the voltage sourced converter based high-voltage direct-current (VSC-HVDC) transmission technology has been widely applied in scenarios including point-to-point transmission, back-to-back inter-connections and DC grids. As a core piece of equipment in VSC-HVDC transmission engineering, the VSC valve achieves AC/DC energy conversion through frequent switching of power electronic devices. In this paper, the key design requirements for VSC valves in different application scenarios are systematically summarized by combining with practical experiences accumulated in engineering, the commonly used power devices and VSC valve topologies in VSC-HVDC transmission engineering are compared and analyzed, and their development trends are projected. In addition, different schemes for two typical application scenarios in the future are also compared, providing reference for the applications of VSC-HVDC transmission technology in high-voltage, large-capacity and long-distance transmission scenarios.

Power semiconductor devices are the core of electric energy conversion and electric drive based on the power electronics technology, which have broad application prospects in new energy generation, transportation, aerospace and other fields. However, the problems such as degradation, failure and reliability caused by heat generation have become bottlenecks that limit their further development, and it is urgent to explore effective thermal management methods to improve their reliability and service life. In this paper, based on the introduction of thermal management methods for power modules, the research progress in active thermal management methods is reviewed in detail, and these methods are divided into device-level, system-level and multi-parameter comprehensive methods according to the difference in control parameters. In addition, various methods are analyzed and compared. Finally, the development trend and prospect of technologies for power devices which are related to junction temperature are put forward, providing a reference for the subsequent research and applications.

The bidirectional switch is extensively applied in the fields such as state-solid breakers and photovoltaic inverters, and increasing attention is paid to the bidirectional switch of SiC power modules owing to its low power loss and high switching frequency. However, due to the traditional packaging methods for Si power modules, the bidirectional switch of the SiC power module is challenged by the issue of high switching speed. Aimed at the low-inductance packaging requirement, a chip-on-chip 3D packaging method is proposed for the bidirectional switch of the SiC power module. The circuit topology and geometric structure of the 3D packaging are given, and the communication loop and parasitic inductance of the 3D packaging are analyzed. In addition, the process was designed for the 3D packaging, and a prototype of the bidirectional switch of the SiC power module was fabricated. Experimental results of a double-pulse test verified the feasibility and effectiveness of the proposed 3D packaging for the bidirectional switch of the SiC power module.

Enhancing the power density of vehicle-grade power modules is of significance for the performance of electric vehicles. The two-dimensional layout used in conventional power modules results in large parasitic inductance, which limits the switching speed and bus voltage and further affects the increase in power density. To solve this problem, an IGBT power module with EconoDUAL packaging was taken as the research object, and a three-dimensional layout was designed using the stacked DBC method to develop a 1 200 V/1 200 A IGBT power module. The layout structure of the proposed power module was introduced in detail. Compared with those obtained using the conventional two-dimensional layout methods, the parasitic inductance decreased by 58%. Additionally, electrical performance tests including a double-pulse test with pulse current of 1 200 A under bus voltage of 800 V were conducted on the power module, thereby verifying the improved power density of the module. To maintain the heat dissipation performance while increasing the power density,

Owing to their advantages in switching speed, temperature characteristics and voltage withstand capability, silicon carbide (SiC) power modules are gradually applied in the motor controllers of electric vehicles. As a core component of electric vehicles, the motor controller demands high electro-thermal characteristics of power modules, posing a significant challenge to SiC packaging. In this paper, the mainstream HybridPACK Drive module packaging is taken as an example, the driver and direct bonded copper(DBC) layout are optimized, and the copper wire bonding technology is introduced to balance the module's electro-thermal performance and reliability. In addition, the response surface methodology is used to optimize the elliptical Pin-Fin heat sink, thereby enhancing the module's heat dissipation performance. Finally, prototypes of SiC power modules before and after optimization were fabricated for comparison, and a double-pulse test setup and a power back-to-back test setup were established respectively to evaluate the electro-thermal performance of the two approaches. Experimental results indicate that when the chip spacing was equal to half the die width, the optimized power module can achieve a superior thermal performance while maintaining the electrical characteristics.

Silicon carbide(SiC) MOSFETs are widely used in high-voltage, high-frequency and high-power-density applications for new energy electric vehicles owing to their superior material properties. During the process of double-sided cooling, the effect of chip layout spacing on heat dissipation and chip temperature uniformity was usually ignored, and the effect of chip temperature uniformity on the parallel current uniformity of multiple chips was not taken into account. A double-sided cooling package structure was designed, the effect on chip temperature uniformity due to chip layout spacing was analyzed, and the influences of different junction temperatures and different chip layouts on parasitic parameters and switching characteristics were also discussed. Aimed at different chip layout spacings and different cooling conditions, the effectiveness of the proposed method was verified through a large number of simulations and the response face analysis and comparison, providing technical method guidance and quantitative analysis for the influences of SiC power module packaging on chip temperature uniformity and switching characteristics.

As a novel and extensively applied switching device, silicon carbide metal-oxide-semiconductor field-ef fect transistor(SiC MOSFET) offers a faster switching speed and lower device loss in practical applications, thereby en-hancing the converter efficiency and delivering a superior performance. Aimed at the driving characteristics of SiC MOS-FET, the influence of parasitic parameters on its performance was analyzed. To investigate the relationship between the gate-source voltage and turn-on time of SiC MOSFET, a two-pulse experimental platform was also established. However, there are certain drawbacks with the existing domestic SiC MOSFET. Based on the experimental platform and other power products, the changes in conduction time, driving loss and negative voltage amplitude after replacing the imported SiC MOSFET with domestic devices were analyzed.

AC-DC Buck-type power factor correction (PFC) converters are widely applied in low-voltage scenarios. However, they typically suffer from low power factor(PF) and high total harmonic distortions of input current(THDi) caused by the input current dead zones. To solve this problem, firstly, a high PF Buck-type bridgeless PFC converter with hybrid operation modes is proposed by introducing a Buck-Boost converter cell, which operates in the Buck and Buck-Boost modes in the positive and negative half-line cycles, respectively. Although the Buck-Boost cell's efficiency is inferior to that of the Buck cell, the proposed converter can operate in the Buck-Boost mode in the negative half-line cycle, thereby minimizing the dead zones to improve PF and reduce THDi. The proposed converter operates in the Buck mode in the positive half-line cycle, inheriting the high efficiency of the Buck cell. Secondly, the operation modes and PF of the proposed bridgeless converter are analyzed to show its high PF feature. Finally, simulations and experimental tests were conducted to verify the feasibility and theoretical analysis of the proposed converter, and a comparison of performance between the proposed and conventional Buck-type PFC converters was also performed.