To address overheating risks in 3D stacked packaged chips caused by increased power consumption，a thermal resistance matrix-based method was proposed for junction temperature prediction，thereby supporting thermal design and management. A DDR3stacked chip was selected as the case study. Instead of relying on traditional experimental measurements，simulation modeling was utilized to obtain thermal characteristic parameters. Through structural analysis of the 3D configuration，a simulation model was developed using Icepak software. A JESD51-2-compliant thermal test environment was designed to characterize the thermal resistance matrix. Junction temperatures of each chip layer under varying conditions were predicted，and the results demonstrate prediction errors of less than 1% compared to simulation results. This method enables efficient thermal characterization and provides valuable insights for thermal management of 3D stacked chips.

In recent years，tungsten oxide（WO₃）nanomaterials have garnered significant attention in the field of gas sensors. However，their practical applications are limited by drawbacks such as high operating temperatures and low sensitivity. A series of MoS₂/WO₃ nanocomposites were synthesized via a hydrothermal method. Gas-sensing tests for nitrogen dioxide（NO₂）demonstrated that these composites exhibit excellent sensing performance over a working temperature range of 20-180℃ and an NO₂ concentration range of 1ppm-100ppm. Notably，the MoS₂/WO₃ composite with a 2% MoS₂ doping ratio achieved a remarkable response value of 1123.19 toward 20ppm NO₂ at 140℃—seven times that of pure WO₃ at its optimal working temperature（80℃）. Characterization and mechanistic studies revealed that the combination of MoS₂ and WO₃ forms a p-n heterojunction，inducing a charge depletion layer at the interface. Additionally，the band bending effect reduces the energy barrier for gasmolecule adsorption，thereby enhancing both the gas adsorption capacity and surface reaction activity of the composite. This study provides a novel material design strategy and technical approach for developing high-performance，low-temperature NO₂ gas sensors.

Addressing the issues of power-on interference pulses and dV/dt noise in gate drivers for brushless direct current motors，a high-reliability，low-power gate driver with a certain degree of dV/dt noise immunity was designed. The implemented circuit employs a high-side PMOS architecture，ensuring sufficient dead-time by feeding back the gate voltage to two sets of latches. An SR latch incorporating intentional skew design was implemented and combined with the preceding logic stage to suppress dV/dt-induced noise. In the level-shifting circuit，both current mirror and capacitive coupling structures were used to achieve voltage feedback from the high side to the low side while adaptively adjusting the input narrow pulse width. The addition of a power-on detection module resolves interference pulses generated during initial power-on，enhancing robustness and reducing power consumption. The proposed gate driver was fabricated in a 0.25 μm process and operates with a supply voltage range of 30V to 60V. At 25 ℃ in the typical process corner，aminimized dead time of approximately 12ns is achieved while driving a 1A current-capable power stage with a multi-stage buffer，ensuring dead-time sufficiency is maintained.

Since hafnium-oxide-based ferroelectric tunnel junctions are compatible with the standard CMOS process，they have great application potential in the field of random access memory. The tunneling electroresistance effect in TiN/HZO/Pt ferroelectric tunnel junctions was rigorously analyzed using the Airy function. The theoretical results indicate that: when the bias voltage is high，the tunneling conductance and Tunneling Electroresistance Ratio（TER）will oscillate with both the bias voltage and the thickness of tunneling layer. Physically，the oscillations originate from the interference between the incident and reflected electron waves in the tunneling layer. The theoretical analysis indicates the physical mechanism underlying the experiments in hafnium oxide-based ferroelectric tunnel junctions. In addition，when the bias voltage is applied to the Pt electrode，there exists negative TER. This phenomenon indicates that the tunneling conductance is not only related to the average height of the barrier，but also associated with the potential structure of the tunneling layer. The present work provides a theoretical method for calculating the tunneling electroresistance effect in hafnium oxide-based ferroelectric tunnel junctions，and lays a theoretical foundation for the applications of hafnium oxide-based ferroelectric tunnel junctions in the field of random access memory.

Low Temperature Co-fired Ceramics（LTCC）technology is recognized as one of the most promising three-dimensional packaging technologies. As the pastes used in LTCC technology evolve from gold to silver and copper，electroless Ni/Pd/Au（ENEPIG）plating has become a crucial step to prevent post-sintering oxidation or electromigration failures of embedded circuits. Based on this context，this study comprehensively reviews the corrosion mechanisms of LTCC substrates in acidic/alkaline environments. Typical corrosion behaviors and failure cases are analyzed to reveal their common degradation patterns. The intrinsic relationships among the composition，structure，and corrosion resistance of LTCC sintering additive glasses under diverse corrosive conditions are systematically summarized. Furthermore，design principles for sintering additive glasses applicable to electroless-plated LTCC substrates are discussed，providing theoretical guidance for developing low-cost and high-reliability LTCC materials.