The health monitoring of the IGBT is crucial for the normal operation of the system, and current research mainly focuses on single aging. The combination of multiple aging states can lead to low applicability and misoperation of some monitoring methods. There are still many shortcomings in the research on the determination and differentiation of multiple aging states. Due to the rich information contained in the U_CE spectrum, different aging will have different effects on it. Therefore, a method for determining and distinguishing bond wire aging and gate aging based on U_CE spectrum is proposed. Firstly, the impact of bonding wire and gate aging on the voltage switch waveform is analyzed. Then, fast Fourier transform (FFT) the switch voltage waveform and perform spectral analysis to explore the impact of different aging on the spectrum, and thus make aging judgments and distinctions. Finally, the circuit is constructed for experimental verification and the impact of different operating conditions on the method is analyzed. The experimental results show that both bond wire aging and gate aging can increase the amplitude of the high-frequency band, and the proposed method can effectively distinguish different aging forms.

The power module is a critical component of the powertrain system in electric vehicles, and its development is driven by the trends of high-frequency operation, miniaturization, high power density and high integration, which brings increasingly severe challenges to thermal management. Thermoelectric cooler (TEC) has attracted widespread attention for its compact structure, high reliability and rapid cooling performance. A temperature feedback control strategy based on thermoelectric cooling is proposed, with phase change materials (PCM) adopted as the interface layers at both cold and hot ends of TEC. Combined with simulation and experimental verification, the layout design of transverse and longitudinal heat transfer paths from the chip to the heat sink is investigated. Compared with the non-TEC cooling scheme, the proposed integrated TEC-based thermal management method reduces the maximum temperature of the SiC chip from 77.6 ℃ to 60.0 ℃, achieving effective thermal regulation and precise temperature feedback control. An efficient thermal management solution for high-power-density SiC power modules is provided and its application potential in electric vehicle power systems is exhibited.

A gallium nitride high electron mobility transistor (GaN HEMT) is widely used in switching power supply design because of its superiority over silicon devices in terms of switching speed, switching loss, and power conversion. Due to the high di/dt and du/dt of GaN HEMT in the switching process, the gate-source of the device in the bridge circuit is easily affected by the parasitic parameters to generate excessive voltage oscillation, which will seriously affect the safety and reliability of the system. To address the above problems, firstly, the bootstrap driver circuit of GaN HEMT is constructed, the mechanism of oscillation is analyzed, and then the RCD circuit based on GaN HEMT is proposed to suppress the negative voltage spike caused by voltage oscillation. Finally, a pulse test circuit is built to experimentally verify the suppression effect of the RCD circuit. Compared with the traditional bootstrap driver circuit, the negative voltage spike after adding the RCD circuit changes from -3.35 V to -1.20 V, and there is no significant delay in the turn-on time of the turn-on process and the turn-off loss process is reduced. The above experimental results verify the effectiveness of the RCD circuit for directional suppression of gate-source oscillation.

Traditional energy storage systems typically include a charging/discharging converter and an equalizer, which are independent of each other. To reduce system complexity and the number of components, a converter for energy storage systems is proposed, which integrates an equalizer into a charge/discharge converter, and achieves automatic voltage balancing between series-connected batteries without the need for voltage measurement circuits, thereby reducing components and simplifying the system. There are two types of proposed converters: type A contains only one active switch, one n-winding inductor and n diodes; type B replaces n diodes in type A with n active switches to improve the efficiency of the circuit. The similarities and differences between type A and type B converter are comparable to those between the asynchronous and the synchronous Buck converter, type B is mainly analyzed and developed a prototype. The experimental results indicate that the proposed converter has good voltage balancing characteristics.

Traditional CLLLC resonant converters do not effectively utilize the switching tubes of the rectifier circuit during operation, resulting in current flowing only through their anti-parallel diodes, leading to high losses and low efficiency. The traditional synchronous rectification scheme based on drain-source voltage is susceptible to the influence of parasitic inductance of switching tubes at high frequencies, which affects the efficiency of synchronous rectification. A detailed analysis of the impact of parasitic parameters on the duty cycle and efficiency of synchronous rectification in CLLLC resonant converters is provided, and an optimization strategy for synchronous rectification based on drain-source voltage is proposed. In a CLLLC resonant converter, the strategy adjusts the turn-off threshold voltage of secondary MOSFET, and improves the efficiency of synchronous rectification by compensating the duty cycle loss time of the synchronous rectifier switching tubes. The experimental results show that the synchronous rectification optimization strategy proposed can effectively reduce the duty cycle loss caused by parasitic parameters and lower the overall losses of CLLLC resonant converter, compared with the traditional synchronous rectification strategy based on drain-source voltage.

The dual active bridge (DAB) microinverter employs a transformer for isolation and step-up before connecting to the grid through bidirectional switches and cycloconverter operation. In comparison to other microinverter solutions, this design boasts numerous advantages, including high conversion efficiency, a broad soft-switching range, a reduced number of power conversion stages, and the ability to provide reactive power support. First, in terms of circuit modulation and control, the circuit topology and switching stages of the DAB DC-AC converter are thoroughly analyzed, a time-domain model is established, the range of transmitted power and soft-switching range are provided, and a feasible closed-loop control framework is proposed. Then, for hardware design, the primary passive components of the DAB microinverter include transformers and inductors. To further enhance power density, a magnetic integration design for transformers and inductors is introduced. By constructing additional magnetic paths on the microinverter transformer, the inductance value of the integrated inductor can be flexibly adjusted, significantly reducing the volume of magnetic components. Finally, a 450 W experimental prototype was built, and experiments were conducted to validate the effectiveness and feasibility of the proposed modulation strategy and magnetic component design method.

An embedded feedforward ripple cancellation (EFFRC) technology with a low-pass filter is proposed to address the issue of poor power supply rejection (PSR) performance in traditional output-capacitorless low-dropout regulator (LDO) operating in the medium and high frequency range. Firstly, an adaptive bias super source follower is inserted into a cascaded flipped voltage followers to drive the power transistor, and Miller compensation and feedforward capacitance compensation techniques are employed to ensure system stability and widen the LDO loop bandwidth. Additionally, a dedicated low-pass filter is integrated into the buffer to effectively eliminate power ripples at the LDO output without consuming additional power, thereby significantly enhancing PSR frequency characteristics. The designed LDO is implemented using SMIC130 nm CMOS process. Simulation results demonstrate that it achieves a low-frequency PSR value of 90 dB across a load change ranging from 0 to 50 mA. Furthermore, the PSR exhibits a frequency bandwidth exceeding 10 MHz, with potential improvements of up to 12 dB in the mid-frequency band. The good PSR characteristics show that the LDO has good dynamic suppression ability for different-frequency noise of input voltage, so it can provide a clean power supply voltage for the circuit driven by it, such as high-performance analog-to-digital converters and low-noise amplifier.

In the process of engineering implementation, the dead-beat current tracking control actually evolves into a one-beat lag control, which leads to the decline of harmonic compensation performance of active power filters. On the basis of analyzing the influence of system delay on digital control, adaptive forward linear prediction and repetitive prediction algorithms are prehensively used to predict the harmonic compensation reference current two sampling times in advance, and discriminant conditions for the switching of the two prediction algorithms are set based on whether the system dynamics occurs. In order to predict the output current of the inverter at one sampling times in advance and effectively suppress the measurement noise, the inverter current prediction link uses both the harmonic reference current to be compensated and the historical data of the output current as inputs. Therefore, the stability of the proposed predictive dead-beat control is analyzed when the output filter inductance and resistance parameters of the main circuit are deviated, and the transmission of current and voltage measurement noise in the system is further analyzed. Finally, simulation and experimental comparison studies on three types of predictive dead-beat control are conducted to verify the effectiveness of the mixed current prediction-based dead-beat control algorithm proposed.

Synchronous compensator can effectively improve the oscillation problem caused by renewable energy connected to a weak grid, but most of the existing regulator modeling methods for oscillation analysis do not take into account the control role of the excitation regulator, which is not accurate enough when applied to the analysis of low-frequency power oscillations, resulting in the limited scope of application of the model. For this reason, a synchronous compensator impedance modeling method that takes into account the excitation response characteristics is proposed. Firstly, a general impedance model of synchronous machine is established. Then, the influence of the self-shunt static excitation system on the impedance characteristics of the compensator is analyzed, and the overall impedance model of the compensator is obtained by associating the excitation model with the synchronous machine model. Finally, the validity of the proposed method is verified by simulation cases, and the analytical results show that: the impedance of the compensator will peak near the industrial frequency (corresponding to low power frequency), and the excitation system will significantly reduce the peak impedance; the self-parallel static excitation system will significantly change the impedance around the power frequency, so that the impedance will be characterized by multiple peaks.

Single-phase phase-locked loop (PLL) is widely used in fields such as power systems. However, the traditional single-phase PLL algorithms face challenges such as high computational complexity and complicated calculation methods. Moreover, their performance is affected in scenarios where the frequency of the input signal undergoes significant changes. A single-phase phase-locked loop based on sinusoidal tracking nonlinear control is proposed to address these issues. Using a Lyapunov stability-based design method, global convergence is achieved when the input signal frequency changes. A simulation model of this new PLL is constructed in PSIM and the application effects of the proposed method are compared with the conventional single-phase PLL based on the second-order generalized integrator, an experimental test is completed using the TMS320F28069 digital signal processor. Simulations and experiments indicate that the algorithm, with its simplicity and fast response, can improve the accuracy degradation issue occurring in traditional second-order generalized integrators during abrupt frequency changes.