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A Configurable Multi Input Port Hybrid Inverter Topology With Quadrupled Voltage Gain for PV and Hybrid Applications
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Baibhav Kumar GUPTA, Aashish KUMAR, K. Ramachandra SEKHAR
CPSS Transactions on Power Electronics and Applications | 2024, 9(4) : 361 - 372
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CPSS Transactions on Power Electronics and Applications | 2024, 9(4): 361-372
• Original articles •
A Configurable Multi Input Port Hybrid Inverter Topology With Quadrupled Voltage Gain for PV and Hybrid Applications
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Baibhav Kumar GUPTA, Aashish KUMAR, K. Ramachandra SEKHAR
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  • Indian Institute of Technology Ropar Department of Electrical Engineering Rupnagar 140001 India

    • Baibhav Kumar Gupta earned his B.Tech. in Electrical and Electronics Engineering from Dr. M.G.R University, Chennai, India, in 2013, followed by an M.Tech. in Electrical Engineering from the Birla Institute of Technology, Mesra, India, in 2016. He completed his Ph.D. at the Indian Institute of Technology Ropar in January 2023 and subsequently served as a Research Associate on a Ministry of Electronics and Telecommunications project at IIT Ropar. Currently, he is an Assistant Professor at the School of Engineering and Applied Science at Ahmedabad University. His research focuses on innovative grid interconnection topologies that reduce DC bus voltage requirements and facilitate grounding. Additionally, he explores power quality issues, circulating currents, MPPT tracking, active filtering, and harmonics mitigation in grid-coupled solar inverters.

    Aashish Kumar received the B.Tech. degree in electrical and electronics engineering from G.K.V, Harid war, India, in 2016, and the M.E. degree in electrical engineering in 2020 from IIT Ropar, India, where he is currently working toward the Ph.D. degree with Electrical Engineering Department. His research primarily focuses on modeling and controlling power converters for renewable energy sources. He also investigates various MPPT tracking algorithms to optimize power extraction, as well as active filtering and harmonics mitigation in grid-coupled solar inverters.

    K. Ramachandra Sekhar received the B.E. degree in electrical and electronics engineering from the University of Madras, Chennai, India, in 2004, the M.E. degree in power electronics and drives from Anna University, Chennai, India, in2006, and the Ph.D. degree in power electronics from the Electrical Engineering Department, IIT Hyderabad, Hyderabad, India, in 2013. From 2013 to 2017, he was with R&D Division, Hitachi, as a Researcher. Since 2017, he is currently working as an Assistant Professor with the Electrical Engineering Department, IIT Ropar, Ropar, India. His research interests include design and implementation of high energy density converters for utility grid/microgrid, control techniques for the power converter, power quality assessment, and EMC/EMI analysis.

Published: 2024-12-10 doi: 10.24295/CPSSTPEA.2024.00020
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The presented work demonstrates the threeport inverter configuration for a quadrupled reduction in the operating DC bus voltage compared to conventional inverter topology. Thus, the proposed configuration consists the single inversion stage and operates with single or multiple sources. Irrespective of the source connected at input ports, the three inverters in the triinverter configuration synthesize the 512 switching combinations and spread across 61 voltage space locations to realize the load space vector. The switching states are segregated from the space spread not only to realize the maximum voltage gain but also to eliminate the common mode voltage during common DC source operations. In the case of common DC source operation, the CMV eliminated switching combinations ensures the elimination of circulating current with minimum compromise of the voltage gain. The improved voltage gain and eliminated circulating current guarantees the maximum energy yield from source and improved reliability of the converter compared to the conventional inverter. The proposed converter's efficacy and realized space vector switching states in terms of realizable four times voltage gain and the elimination of intrainverter circulating currents are validated experimentally with single and multiple sources.

A multi-port network  /  common DC bus  /  configurable input ports  /  hybrid photovoltaic systems  /  inverter topology  /  renewable energy sources  /  voltage gain
Baibhav Kumar GUPTA, Aashish KUMAR, K. Ramachandra SEKHAR. A Configurable Multi Input Port Hybrid Inverter Topology With Quadrupled Voltage Gain for PV and Hybrid Applications[J]. CPSS Transactions on Power Electronics and Applications, 2024 , 9 (4) : 361 -372 . DOI: 10.24295/CPSSTPEA.2024.00020
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I. Introduction
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THE power electronic converters are well suited for modul- ating the renewable energy in accordance with the load demand characteristics for efficient energy harvesting. The abundance, ease in installations and global political scenarios make the solar energy is an attractive green generation option among renewable sources. But the intermittent solar nature demands appropriate power converters topologies operate in hybrid mode with multiple energy and storage systems.
Therefore in recent, a multi input power converters are getting attention of researchers to prepare customized hybrid interfaces aiming to maximize the PV energy yield and ensure seamless power to the load as per the demand [1]-[5]. However, the major challenge is arbitrating the source characteristics for maximized efficiency, cost optimization and instantaneous load demand. In general PV panel exhibits the current source characteristics, thus it offer better energy yield at low voltage and high current. Contrary AC loads operate at high voltage and low current to achieve the optimized efficiency, thus inversion stage demands the higher DC voltage to synthesize the load AC voltage. To accomplish the required DC bus voltage, the researchers have suggested either step-up converters or PV panel interconnections at the inverter’s input terminals. With the use of boost converters at the input terminals make the inverter configuration double stage. Even in two stage conversion, the limitations associated with the DC-DC converters in terms of voltage boost, the researchers have used either cascaded boost typologies or boost converter with sufficiently boosted input voltage through source (PV strings) interconnections to derive the demanded DC voltage for the inverter [6]-[14]. In the case of cascaded DC-DC converter configurations, the two or more number DC voltage conversion stages demands the complex synchronized stage algorithms for efficient voltage boost, and involved switching devices along with passive filter elements make the system less viable for industry adoption. Considering the drawbacks associated with the double stage conversion, past researchers have derived the DC bus voltages by connecting the PV strings/batteries in series at the input terminals, makes the inverter topology single stage [15]-[22]. In this case, although the requirement of the DC-DC converters is eliminated, the elevated DC potentials across the PV string negatively influence the life of solar panels and energy-yielding capacity during partial irradiation due to potential induced degradation effect and total number of involved panels per string, respectively [23].
In hybrid source applications with the double stage configurations, the DC converters are connected in parallel to feed to the common inversion stage. In the case of single-stage conversion typologies, the inverters are connected in parallel to feed to the single AC load/grid. However, the parallel typologies, the common DC (double stage) and AC (single-stage) coupling, attract the intramodular circulating current due to uncertainties in the instantaneous switching, control signal propagation delay, and impedance mismatch [24]-[26]. Since the common mode voltages between the converters are root cause for the circulating current, it is required to analyze the magnitude and frequency of the common mode voltage to cease/reduce the circulating current, thus to improve the thermal performance of the converters.
Apart from the circulating current in a parallel configuration, the other serious concern is the demand for bulky electrolytic capacitors with elevated DC potential at the input terminals [8]-[10],[18],[19]. The electrolytic capacitor generally has a short life span with a steep detrimental performance gradient and occupies more design space that adds to the overall weight, size, and cost of the inverter. At higher DC potential, the DC capacitors required to handle the higher voltage ripple acts as weak links in determining the system reliability and negatively influence the conversion power density of the configuration. Although the past researchers have tried to reduce the failure rate of the configuration and improve power density by reducing the DC link capacitor size [10],[19] but at the cost of demanded capacitance during uncertainties and over voltage scenarios. Since these methods are not addressing the root cause of the problem which is higher DC bus voltages, the recommended solutions can be seen as partial solutions. To overcome the associated draw backs, it is required to reduce the operating potentials of the DC bus of inverter terminals.
This research introduces a novel tri-port voltage-sharing topology designed for hybrid source applications, addressing drawbacks found in existing typologies. The proposed configuration is adaptable for operation with both isolated and common DC sources, achieving maximum quadrupled voltage conversion gain through strategic switching. When connected to a common DC source, a comprehensive common mode voltage (CMV) analysis is crucial for selecting optimal switching states to achieve zero CMV. The categorization of switching states based on voltage gain and CMV magnitudes, derived through thorough analysis, enables multi and single source operations. Experimental validation against single and dual inverter typologies demonstrates the effectiveness of the proposed configuration, which, while demonstrated for ${50}\mathrm{\;{Hz}}$ applications, is versatile enough to accommodate any fundamental frequency by adjusting the reference space vector frequency. Additionally, the proposed configuration would attract the industry attention in the future due to the following associated advantages:
1) Ability to operate with single or multiple DC sources.
2) The reduced DC bus potential would ease the potential induced degradation (PID) effect on the solar panel that would improve solar panel life.
3) The minimum number of solar panels connected in series to derive the DC bus ensures the integrity of lower power applications compared to single-stage inverter topologies.
4) Due to lower DC bus requirement with the proposed configuration improves the MPPT efficiency during partial irradiation conditions.
5) The minimum DC bus voltages across the switching devices would ensure to go for maximum switching frequency.
6) The common-mode voltage elimination provides the flexibility to ground the DC bus.
II. The Proposed Hybrid Tri-Input Port Single Stage Inverter Configuration
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The proposed tri-input port single stage inverter configuration interfaced with the three phase load through three phase transformer as shown in Fig. 1. At the primary of the transformer, the derived center tapped winding (d-e and e-f) connected with the individual phases of tri-inverters. As it is shown in Fig. 1, the a-phase of the three inverter terminals ${a}_{1},{a}_{2}$ and ${a}_{3}$ connected with transformer terminals ${d}_{a1}$ and ${e}_{a2}$ and ${\mathrm{f}}_{\mathrm{a}3}$ respectively. Similarly, the three inverter b-phase pole mid points (b1, b2,and b3) and c-phase pole mid points (c1, c2,and c3) are connected with the transformer primary winding terminals ${\mathrm{d}}_{\mathrm{b}1},{\mathrm{e}}_{\mathrm{b}2},{\mathrm{f}}_{\mathrm{b}3}$ and ${\mathrm{d}}_{\mathrm{c}1},{\mathrm{e}}_{\mathrm{c}2}$ and ${\mathrm{f}}_{\mathrm{c}3}$ respectively. At the secondary of the transformer, the three phase load connected with the terminals ${\mathrm{g}}_{\mathrm{a}},{\mathrm{g}}_{\mathrm{b}}$ and ${\mathrm{g}}_{\mathrm{c}}$ and other end of the three phase secondary winding forms the neutral point as shown in Fig. 1. In this configuration, the three inverters connected with common/isolated DC sources collectively feeding to common AC load. Since the three inverters are involved in proposed configuration, with each inverter contribute ${2}^{3}$ switching combination, combined ${2}^{3}\times {2}^{3}\times {2}^{3}= {512}$ switching combinations can be realized to synthesize the AC voltage across the load. Depending upon the switching combination of the proposed configuration, the realizable voltage space vector on transformer primary winding (d-e and e-f) and the load can be derived as:
Across primary winding (d-e) with Inverters 1 and 2 (Fig. 1)
${V}_{{\mathrm{{de}}}_{\mathrm{{abc}}}}= {V}_{\mathrm{{dc}}}\left\lbrack {\left({{S}_{\mathrm{a}1}- {S}_{\mathrm{a}2}}\right){\mathrm{e}}^{\mathrm{j}0}+ \left({{S}_{\mathrm{b}1}- {S}_{\mathrm{b}2}}\right){\mathrm{e}}^{\mathrm{j}{120}}+ }\right.$
$\left.{\left({{S}_{\mathrm{c}1}- {S}_{\mathrm{c}2}}\right){\mathrm{e}}^{\mathrm{j}{240}}}\right\rbrack $
Across primary winding (e-f) with Inverters 2 and 3 (Fig. 1)
${V}_{{\mathrm{{ef}}}_{\mathrm{{abc}}}}= {V}_{\mathrm{{dc}}}\left\lbrack {\left({{S}_{\mathrm{a}2}- {S}_{\mathrm{a}3}}\right){\mathrm{e}}^{\mathrm{j}0}+ \left({{S}_{\mathrm{b}2}- {S}_{\mathrm{b}3}}\right){\mathrm{e}}^{\mathrm{j}{120}}+ }\right.\\\left.{\left({{S}_{\mathrm{c}2}- {S}_{\mathrm{c}3}}\right){\mathrm{e}}^{\mathrm{j}{240}}}\right\rbrack $
${V}_{\text{gabc }}= {V}_{\mathrm{{dc}}}\left\lbrack {\left({{S}_{\mathrm{a}1}- 2{S}_{\mathrm{a}2}+ {S}_{\mathrm{a}3}}\right){\mathrm{e}}^{\mathrm{j}0}+ \left({{S}_{\mathrm{b}1}- 2{S}_{\mathrm{b}2}+ {S}_{\mathrm{b}3}}\right){\mathrm{e}}^{\mathrm{j}{120}}}\right.\\\left.{+\left({{S}_{\mathrm{c}1}- 2{S}_{\mathrm{c}2}+ {S}_{\mathrm{c}3}}\right){\mathrm{e}}^{\mathrm{j}{240}}}\right\rbrack $
where ${S}_{\mathrm{a}1},{S}_{\mathrm{b}1},{S}_{\mathrm{c}1}$ are switching states of Inverter- $1,{S}_{\mathrm{a}2},{S}_{\mathrm{b}2},{S}_{\mathrm{c}2}$ are switching states of Inverter-2, ${S}_{\mathrm{a}3},{S}_{\mathrm{b}3},{S}_{\mathrm{c}3}$ are switching states of Inverter-3. The individual switch can attain either 1 (top switch of the leg is $\mathrm{{ON}}$) or0(bottom switch of the leg is $\mathrm{{ON}}$) and further, the top switch is complementary with the bottom switch. By substituting 512 switching combinations in (3), 61 space locations can be realized as shown in Fig. 2. For instance, the switching combination 1(100) with Inverter-1, 4’(011) with inverter-2 and 1”(100) with Inverter-3, the voltage at the load can be realized through (3) as $4{V}_{\mathrm{{dc}}}\angle 0$. Although the derived switching combination can exhibit the voltage gain up to 4 compare to conventional topology, the interconnection of the inverter through winding demand inter-inverter influential voltage (known as common mode voltage (CMV)) analysis of each switching state. In this work, the CMVs across the individual inverter (capacitor mid point) and the ground due to simultaneous switching of inverters in proposed configuration can be derived as:
${\mathrm{{CMV}}}_{{\text{inv }}_{\mathrm{{lg}}}}= \frac{1}{9}\left\lbrack {\left({{S}_{\mathrm{a}1}- {S}_{\mathrm{a}2}}\right)+ \left({{S}_{\mathrm{a}1}- {S}_{\mathrm{a}3}}\right)+ \left({{S}_{\mathrm{b}1}- {S}_{\mathrm{b}2}}\right)}\right.$
$\begin{aligned}\mathrm{CMV}_{\mathrm{inv}_{2 \mathrm{g}}}= & \frac{1}{9}\left[\left(S_{\mathrm{a} 2}-S_{\mathrm{a} 1}\right)+\left(S_{\mathrm{a} 2}-S_{\mathrm{a} 3}\right)+\left(S_{\mathrm{b} 2}-S_{\mathrm{b} 1}\right)\right. \\& \left.+\left(S_{\mathrm{b} 2}-S_{\mathrm{b} 3}\right)+\left(S_{\mathrm{c} 2}-S_{\mathrm{c} 1}\right)+\left(S_{\mathrm{c} 2}-S_{\mathrm{c} 3}\right)\right]\end{aligned}$
$\begin{aligned}\mathrm{CMV}_{\mathrm{inv}_{\mathrm{3g}}}= & \frac{1}{9}\left[\left(S_{\mathrm{a} 3}-S_{\mathrm{a} 1}\right)+\left(S_{\mathrm{a} 3}-S_{\mathrm{a} 2}\right)+\left(S_{\mathrm{b} 3}-S_{\mathrm{b} 1}\right)\right. \\& \left.+\left(S_{\mathrm{b} 3}-S_{\mathrm{b} 2}\right)+\left(S_{\mathrm{c} 3}-S_{\mathrm{c} 1}\right)+\left(S_{\mathrm{c} 3}-S_{\mathrm{c} 2}\right)\right]\end{aligned}$
The magnitude of the derived CMV using (4),(5) and (6) for all 512 switching states are presented in Fig. 3. Further, it can be observed that the CMV between the individual inverter capacitor mid point and ground can attain 13 voltage levels ((+/-)0.667Vdc, (+/-)0.556Vdc, (+/-)0.445Vdc, (+/-)0.334Vdc, (+/-)0.223Vdc, (+/-)0.112Vdc and 0) as shown in Fig. 3. The existence of CMV between the capacitor mid point and ground restrict the DC bus grounding, thus only switching combinations with the zero common mode voltage (the switching combinations correspond to level ‘L’ shown in Fig. 3) can be used if in case DC bus need to be grounded. Further to operate the two/three inverter with the common DC bus, it is required to analyze the inter-inverter CMV between the inverters for zero influence of three inverters on each other. The inter-inverter CMV can be realized from the individual inverter CMV as:
$\begin{aligned}\mathrm{CMV}_{\mathrm{inv}_{12}} & =\left(\mathrm{CMV}_{\mathrm{inv}_{1 \mathrm{~g}}}-\mathrm{CMV}_{\mathrm{inv}_{2 \mathrm{~g}}}\right) \\& =\frac{1}{3}\left[\left(S_{\mathrm{a} 1}-S_{\mathrm{a} 2}\right)+\left(S_{\mathrm{b} 1}-S_{\mathrm{b} 2}\right)+\left(S_{\mathrm{c} 1}-S_{\mathrm{c} 2}\right)\right]\end{aligned}$
$\begin{aligned}\mathrm{CMV}_{\mathrm{inv}_{23}} & =\left(\mathrm{CMV}_{\mathrm{inv}_{2 \mathrm{~g}}}-\mathrm{CMV}_{\mathrm{inv}_{3 \mathrm{~g}}}\right) \\& =\frac{1}{3}\left[\left(S_{\mathrm{a} 2}-S_{\mathrm{a} 3}\right)+\left(S_{\mathrm{b} 2}-S_{\mathrm{b} 3}\right)+\left(S_{\mathrm{c} 2}-S_{\mathrm{c} 3}\right)\right]\end{aligned}$
$\begin{aligned}\mathrm{CMV}_{\text {inv }_{31}} & =\left(\mathrm{CMV}_{\text {inv }_{3 \mathrm{~b}}}-\mathrm{CMV}_{\text {inv }_{1 \mathrm{~g}}}\right) \\& =\frac{1}{3}\left[\left(S_{\mathrm{a} 3}-S_{\mathrm{a} 1}\right)+\left(S_{\mathrm{b} 3}-S_{\mathrm{b} 1}\right)+\left(S_{\mathrm{c} 3}-S_{\mathrm{c} 1}\right)\right]\end{aligned}$
With scrutiny of each possible switching combinations for three inverters present in the proposed configuration interms of realizable gain and the CMV magnitudes, the switching combinations are categorized for different DC input port configurations as explained in the subsequent sub-section.
A. Case-1: The Three Isolated DC Sources Connected to the Each Input Port of the Three Inverter
In case of isolated DC sources, the electrical isolation between the primary side input ports and floating neutral allow to use all 512 switching combinations. Among 512 switching combinations, the outer hexagon switching locations E1, E5, E9, E13, E17 and E21 shown in Fig. 2 contribute to yield the maximum gain of four and synthesize the rotating magnetic field across the load (secondary of the transformer). Thus these switching combinations can be referred as “four gain” space locations and realization of quadrupled gain with these switching locations is shown in Fig. 4. For an instance, the switching combination 14’1”, the Inverter-1 and Inverter-2 realizes the voltage of $2{V}_{\mathrm{{dc}}}$ on winding d-e (Fig. 1), Inverter-2 and Inverter-3 also realizes the $2{V}_{\mathrm{{dc}}}$ on winding e-f (Fig. 1) that generate the combined $4{V}_{\mathrm{{dc}}}$ across the secondary winding as shown in Fig. 4(a). Similarly the the voltage gain realizations with the other four gain switching locations (E5, E9, E13, E17 and E21) in synthesizing the voltage space vector with the four gain is shown in Fig. 4.
B. Case-2: The Common DC Source Connected With Two Input Ports and Third Port Connected With Isolated DC Source
In case of two DC ports are fed from the common DC bus, it is required to ensure through switching combinations that, the CMV between inverters must be 0 . In case of two inverters sharing the common DC bus, the corresponding switching combinations are categorized using (7)-(9) and presented in Table I based on the common DC bus fed inverter pair. As it is shown in Table I, the group-1 and group-4 switching combinations can exhibit zero CMV ensures the common DC bus for Inverters 1 and 2. Similarly, group-2 and group-4 switching combinations shown in Table I can be used with the shared DC bus between Inverters 2 and 3, and group-3 and group-4 switching combinations are used for common DC bus fed Inverters 3 and 1. Among these switching combinations, the group-1 of table I switching combinations representing the switching locations E4, E8, E12, E16, E20 and E24 (Fig. 2) are chosen to synthesize the rotating voltage vector in space. With these switching locations, the maximum voltage conversion gain of ${3.6}{V}_{\mathrm{{dc}}}$ can be realized across the load with two inverters of the proposed configuration sharing the common DC bus as demonstrated in Fig. 5.
C. Case-3: The Common DC Source Shared With all Three Input Ports of the Inverters
When three inverters are fed from the common DC bus, the CMV voltages between the inverters must be 0 and inverters must operate with the states mentioned group-4 of Table I. Among the group- 4 switching combinations, the switching states correspond to switching locations E3, E7, E11, E15, E19 and E23 of Fig. 2 are identified to yield the maximum voltage conversion gain of ${3.4}{V}_{\mathrm{{dc}}}$ as demonstrated in Fig. 6. From this discussion, it is evident that, the CMV eliminated switching locations can exhibit 13.5% and 3.8% lesser voltage conversion gain compare to case-1 and case-2 respectively.
III. Results and Discussions
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A. Validation Through Simulation
The proposed tri-input port voltage sharing configuration was initially validated through Simulink simulations using the electrical parameters listed in Table II. In these simulations, all three inverters operated with an isolated DC bus of ${100}\mathrm{\;V}$, utilizing the Case-3 switching algorithm. This setup aimed to demonstrate the effectiveness of the proposed configuration in functioning with either a common or isolated DC bus, particularly when source-2 and source-3 are unavailable.
The simulation results are illustrated in Fig. 7. As shown, until $t ={3.1}\mathrm{\;s}$, all inverters operate with isolated DC sources, with the current shared among them, as evidenced by the top, middle, and bottom traces in Fig. 7. At $t ={3.1}\mathrm{\;s}$, source-2 is disconnected and reconnected to source-1, causing Inverters 1 and 2 to share a common DC bus, while Inverter-3 continues to use the isolated DC source. Consequently, the current through source-1 doubles, source-2’s current drops to 0, and source-3’s current remains unchanged. At $t = 6\mathrm{\;s}$, source-3 is also disconnected and connected to the common DC source, resulting in source-2 and source-3 currents dropping to 0, with source-1 carrying the full load current.This transition was tested using the Case-3 algorithm due to its zero CMV, which allows for the safe connection of all DC buses without circulating currents among the inverter modules, as shown in Fig. 8. Additionally, the three phase-to-phase voltages are depicted in Fig. 9， illustrating a modulated square wave shape with a 100V variation, consistent with the 120-degree conduction mode and confirming the zero CMV.The output three phase load voltages and currents, shown in Fig. 10， demonstrate a perfect sinusoidal waveform. This highlights the effectiveness of the proposed configuration in operating with a reduced DC bus compared to conventional methods, and it also provides the flexibility to work with a common DC bus.
B. Validation Through Hardware
To further validate the system, an experimental prototype was developed and tested in the lab, as shown in Fig. 11. The prototype was tested with the electrical parameters listed in Table II across the three cases discussed in the preceding section. In all three cases, the maximum achievable gain and corresponding CMV profiles are validated experimentally as follows.
C. Case-1: Three Inverters Fed From Isolated DC Sources
As in case of three inverters operate with separate isolated DC sources, the switching locations 14’1”(E1), 25’2”(E5), 36’3”(E9), 41’4”(E13), 52’5”(E17) and 63’6”(E21) are used in average to generate the load space vector as shown in Fig. 4 and corresponding a-phase pole voltages of Inverter-1 (Valo), Inverter-2 (Va2o) and Inverter-3 (Va3o) vary between (+/-)50V with the DC bus of 100V across each inverter is shown in top three traces of Fig. 12(a)(a). The below two traces of the Fig. 12(a) shows the primary winding $\mathrm{d}- \mathrm{e}$ and $\mathrm{e}- \mathrm{f}$ (of Fig. 1) voltage vary between $\left({+/- }\right){133}\mathrm{\;V}\left({\frac{3}{4}{V}_{\mathrm{{dc}}}}\right),\left({+/- }\right){66}\mathrm{\;V}\left({\frac{2}{3}{V}_{\mathrm{{dc}}}}\right)$ and 0 correspond to DC bus voltage of ${100}\mathrm{\;V}$. The resulting three phase voltages across the load terminal with peak-peak magnitude of(460V)and corresponding three phase load currents with peak magnitude of $\left({+/- }\right){12}\mathrm{\;A}$ as shown in Fig. 12(b). From the experimental results it is evident that ${100}\mathrm{\;V}\mathrm{{DC}}$ would yield ${460}\mathrm{\;V}$ (p-p) AC with the identified switching locations whereas in conventional parallel inverters ${100}\mathrm{\;V}$ would yield only ${115}\mathrm{\;V}$ (p-p) as demonstrated and compared in Fig. 15(c) that confirms the quadrupled gain with the proposed configuration. As it is depicted in preceding section, the “four gain” switching locations yield the corresponding CMV between the individual inverters DC capacitor mid point and ground depending upon the switching states of the three inverters as shown in Fig. 12(c). The magnitudes of the CMV shown in Fig. 12(c) is close concurrence with the theoretically computed CMV using (4),(5) and (6). For example, the switching state 41’4” exhibits the CMV of (+)11 V $\left({\frac{1}{9}{V}_{\mathrm{{dc}}}}\right)$ across the Inverter-1 DC bus and ground (left trace of Fig.12(c)),(+)22 V (-$\frac{2}{9}{V}_{\mathrm{{dc}}}$) across Inverter-2 DC bus and ground (middle trace of Fig.12(c)) and (+)11 V $\left({\frac{1}{9}{V}_{\mathrm{{dc}}}}\right)$ across the Inverter-3 DC bus and ground (right trace of Fig.12(c)) exactly matches with theoretical computations. Similarly, the CMV between Inverters 1 and 2 (left trace of Fig.12(d)), Inverters 2 an 3 (middle trace of Fig.12(d)) and inverters 3 and 1 (right trace of Fig.12(d)) also confirms the theoretically computed magnitudes using (7),(8) and (9).
D. Case-2: Two Inverters Operate With Common DC Bus
In case of sharing the common DC bus with Inverters 1 and 2, the switching locations from the group- 2 and group-4 of Table I can be used. Among these switching combinations, the switching states 15’2”(E4), 26’3”(E8), 31’4”(E12), 42’5”(E16), 53’6”(E20) and 64’1”(E24) are used to synthesize the load voltage space vector as shown in Fig. 5. The corresponding experimentally obtained a-phase pole voltages of Inverter-1 (Valo), Inverter-2 (Va2o) and Inverter-3 (Va3o) vary between (+/-)50V with the DC bus of ${100}\mathrm{\;V}$ each as shown in top three traces of Fig. 13(a). The primary winding d-e voltage vary between $\left({+/- }\right){100}\mathrm{\;V}$ and $\mathrm{e}- \mathrm{f}$ voltage vary between $\left({+/- }\right){133}\mathrm{\;V}\left({\frac{4}{3}{V}_{\mathrm{{dc}}}}\right),\left({+/- }\right){66}\mathrm{\;V}\left({\frac{4}{3}{V}_{\mathrm{{dc}}}}\right)$ and 0 as shown in the below two traces of the Fig. 13(a). The resulting three phase voltages across the load terminal with peak-peak magnitude of 414 V and corresponding three load currents with the peakpeak magnitude of $\left({+/- }\right){11}\mathrm{\;A}$ are shown in Fig. 13(b). The findings confirm a significant reduction in the DC bus requirement, demonstrating a 3.58-fold decrease compared to the SVPWM-based conventional parallel inverter and a 2.08- fold decrease compared to the per-phase balanced switching-based dual inverter configuration. Further, the common mode voltage patterns illustrated in Fig. 13(c) align with the defined switching states, affirming theoretical consistency. The matching CMV profiles between Inverter-1 DC bus to ground (left trace) and Inverter-2 DC bus to ground (middle trace) underscore the effectiveness of the proposed switching states in connecting the common DC bus for both inverters. The identical CMV profiles between Inverter-1 and Inverter-2 result in 0 circulating current between them, as verified by the CMV measurement shown in the left trace of Fig. 13(d). However, varying CMV between Inverters 2 and 3 and Inverters 3 and 1, as per theoretical computations, are evident in the middle and right traces of Fig. 13(d). Notably, CMV between Inverter-2 and ground and Inverter-3 and ground exists, prohibiting the shorting of Inverter-3’s DC bus with Inverter-2 or Inverter-1. Additionally, grounding the midpoint of the DC bus capacitor is not feasible, as it would result in continual circulating currents between the inverter modules and ground, primarily caused by the presence of common mode voltage (CMV).
E. Case-3: Three Inverters Operate With Common DC Bus
In case of three inverters operate with common DC bus, it is required to choose the switching states from group-4 of Table I. In this case, the switching combinations 15’1”(E3), 26’2”(E7), 31’3”(E11), 42’4”(E15), 53’5”(E19) and 13’1”(E23) are used in average sense to synthesize the load space vector as shown in Fig. 6. The corresponding experimentally obtained a-phase pole voltages of Inverter-1 (Valo), Inverter-2 (Va2o) and Inverter-3 (Va3o) vary between (+/-)50V with the DC bus of ${100}\mathrm{\;V}$ each is shown in top three traces of Fig. 14. In this configuration, the voltage across primary windings $\mathrm{d}- \mathrm{e}$ and $\mathrm{e}- \mathrm{f}$ (refer to Fig. 1) varies within $\left({+/- }\right){100}\mathrm{\;V}$, as depicted in the two traces of Fig. 14(a). The resulting three-phase voltages at the load terminal measure ${390}\mathrm{\;V}\left({\mathrm{p}- \mathrm{p}}\right)$, affirming a voltage gain compared to conventional inverters. Corresponding load currents exhibit a peak-to-peak magnitude of ${10.3}\mathrm{\;A}$, as illustrated in the bottom trace of Fig. 14(b). Moreover, there’s a substantial reduction in the DC bus requirement, with a 3.4-fold decrease compared to SVPWM-based conventional parallel inverters and a 1.96-fold decrease compared to per-phase balanced switching-based dual inverter configurations. With the prescribed switching states, the CMVs of Inverter-1 to ground, Inverter-2 to ground, and Inverter-3 to ground, as evident in the left, middle, and right traces of Fig. 14(c), all register as 0, showcasing the successful elimination of CMV through meticulous switching strategies. This achievement not only ensures a robust system but also opens the door to grounding the midpoint of the DC bus capacitor, thereby contributing to the enhanced lifespan of the solar panel. Furthermore, the instantaneous zero CMV observed between Inverters 1 and 2, Inverters 2 and 3, and Inverters 3 and 1, as illustrated in the left, middle, and right traces of Fig. 14(d), guarantees a complete absence of circulating current, enabling the seamless utilization of a common DC source. F. Comparison of Proposed Configuration With Existing Typologies
1) ${F}_{1}$ (Feature-1): Minimum DC bus voltage requirement to generate 440 V(L-L) AC.
2) ${F}_{2}$ (Feature-2): Converter voltage gain.
3) ${F}_{3}$ (Feature-5): Existence of CMV between the inverter modules.
4) ${F}_{4}$ (Feature-6): Provision of DC bus grounding.
The proposed configuration is compared in this subsection with the conventional single stage inverter and dual inverters configurations in-terms of voltage gain and CMV elimination through proper selection of switching states. The experiments have conducted on the single inverter, dual inverter along with the proposed configuration for synthesizing AC voltage with the same DC bus voltage of ${100}\mathrm{\;V}$. The pole voltage variations in space (X-Y plane) for single inverter, dual inverter and proposed configuration with case-1 is identical as shown in Fig. 15(a) represents the operating DC bus of ${100}\mathrm{\;V}$. The corresponding synthesized AC voltage space variations (X-Y plot) across the load for single inverter, dual inverter and proposed configuration with case-1 is shown in left, middle and right trace of Fig. 15(a). From Fig. 15(a), it is clearly evident that the proposed configuration can exhibit quadrupled gain compare single inverter configuration, and twice that of dual inverter configuration. Although the voltage gain is four times compare to conventional single and dual inverter, the common mode voltage exist between the inverter modules similar to single and dual inverter as shown in Fig. 15(c). But as demonstrated in preceding section, the CMV can be nullified in proposed configuration through appropriate selection of switching states as shown in Fig. 15(d) with the approximate 13.5% compromise in voltage gain as shown in Fig. 15(b) compare to maximum achievable gain of four. Subsequently, the comparison Table III is added to showcase the advantages of the proposed configuration over state-of-the-art topologies, covering aspects such as DC bus requirements, voltage gain, the presence of CMV profile, and DC bus grounding. This comparative analysis underscores the unique benefits and superior performance of the proposed topology, demonstrating its potential for practical applications.
IV. Conclusion
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The hybrid source tri-port inverter proposed in this work is experimentally validated with isolated DC sources for quadrupled voltage gain. It means only 170 VDC bus is required to synthesize the standard AC voltage of 415 V (RMS L-L) reduces the DC bus requirements four times compare to conventional single stage inverters. Further, in this work it is demonstrated that through proper selection of switching states the CMV between the inverters can be eliminated. The eliminated CMV between the inverters provides the flexibility to operate the proposed configuration with common DC bus. Thus the proposed configurable port structure is advantageous for solar PV application wherein the generation and load demand are dynamic in nature.
Funding
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  • Ministry of Electronics and Information Technology(25(2)2021-ESDA)
  • Science and Engineering Research Board(CRG/2020/002958)
References
Less
[1]
S. Jiang F. Z. Peng . "Modular single-phase trans-Z-source inverter for multi-input renewable energy system", in 2012 Twenty-Seventh Annual IEEE Applied Power Electronics Conference and Exposition (APEC), Orlando, FL, USA, 2012. 2107 - 2114,
[2]
M. Amirabadi , H. A. Toliyat , W. C. Alexander . "A multiport AC link PV inverter with reduced size and weight for stand-alone application". in IEEE Transactions on Industry Applications, 2013. 49 (5): 2217 - 2228,
[3]
S. M. Dehghan , M. Mohamadian , A. Yazdian , F. Ashrafzadeh . "A dual-input-dual-output z-source inverter". in IEEE Transactions on Power Electronics, 2010. 25 (2): 360 - 368,
[4]
M. Mao , C. Qian , Y. Ding . "Decentralized coordination power control for islanding microgrid based on PV/BES-VSG". in CPSS Transactions on Power Electronics and Applications, 2018. 3 (1): 14 - 24,
[5]
Y. Yang , A. Sangwongwanich , F. Blaabjerg . "Design for reliability of power electronics for grid-connected photovoltaic systems". in CPSS Transactions on Power Electronics and Applications, 2016. 1 (1): 92 - 103,
[6]
Y.-H. Liao C. -M. Lai . "Newly-constructed simplified single-phase multistring multilevel inverter topology for distributed energy resources". in IEEE Transactions on Power Electronics, 2011. 26 (9): 2386 - 2392,
[7]
P. Thounthong , A. Luksanasakul , P. Koseeyaporn , B. Davat . "Intelligent model-based control of a standalone photovoltaic/fuel cell power plant with supercapacitor energy storage". in IEEE Transactions on Sustainable Energy, 2013. 4 (1): 240 - 249,
[8]
W.-J. Lee S. -K. Sul . "DC-link voltage stabilization for reduced DC-link capacitor inverter". in IEEE Transactions on Industry Applications, 2014. 50 (1): 404 - 414,
[9]
H. Wang F. Blaabjerg . "Reliability of capacitors for DC-link applications in power electronic converters-An overview". in IEEE Transactions on Industry Applications, 2014. 50 (5): 3569 - 3578,
[10]
A. Mallik A. Khaligh . "Intermediate DC-link capacitor reduction in a two-stage cascaded AC/DC converter for more electric aircrafts". in IEEE Transactions on Vehicular Technology, 2018. 67 (2): 935 - 947,
[11]
M. Azizi , M. Mohamadian , R. Beiranvand . "A new family of multi-input converters based on three switches leg". in IEEE Transactions on Industrial Electronics, 2016. 63 (11): 6812 - 6822,
[12]
D. Debnath K. Chatterjee . "Solar photovoltaic-based stand-alone scheme incorporating a new boost inverter". in IET Power Electronics, 2016. 9 (4): 621 - 630,
[13]
E. Serban , F. Paz , M. Ordonez . "Improved PV inverter operating range using a miniboost". in IEEE Transactions on Power Electronics, 2017. 32 (11): 8470 - 8485,
[14]
M. Das V. Agarwal . "Novel high-performance stand-alone solar PV system with high-gain high-efficiency DC-DC converter power stages". in IEEE Transactions on Industry Applications, 2015. 51 (6): 4718 - 4728,
[15]
P. Mohseni , S. H. Hosseini , M. Sabahi , T. Jalilzadeh , M. Maalandish . "A new high step-up multi-input multi-output DC-DC converter". in IEEE Transactions on Industrial Electronics, 2019. 66 (7): 5197 - 5208,
[16]
F. Gao , P. C. Loh , F. Blaabjerg , D. M. Vilathgamuwa . "Dual Z-source inverter with three-level reduced common mode switching", in Conference Record of the 2006 IEEE Industry Applications Conference Forty-First IAS Annual Meeting, Tampa, FL, USA, 2006. 619 - 626,
[17]
S. Jain V. Agarwal . "An integrated hybrid power supply for distributed generation applications fed by nonconventional energy sources". in IEEE Transactions on Energy Conversion, 2008. 23 (2): 622 - 631,
[18]
M. Amirabadi , H. A. Toliyat , W. C. Alexander . "A multiport AC link PV inverter with reduced size and weight for stand-alone application". in IEEE Transactions on Industry Applications, 2013. 49 (5): 2217 - 2228,
[19]
H. Wang , H. S. -H. Chung , W. Liu . "Use of a series voltage compensator for reduction of the DC-link capacitance in a capacitor-supported system". in IEEE Transactions on Power Electronics, 2014. 29 (3): 1163 - 1175,
[20]
H. Keyhani H. A. Toliyat . "Single-stage multistring PV inverter with an isolated high-frequency link and soft-switching operation". in IEEE Transactions on Power Electronics, 2014. 29 (8): 3919 - 3929,
[21]
T. V. Thang , N. M. Thao , J. -H. Jang , J. -H. Park . "Analysis and design of grid-connected photovoltaic systems with multiple-integrated converters and a pseudo-DC-link inverter". in IEEE Transactions on Industrial Electronics, 2014. 61 (7): 3377 - 3386,
[22]
A. M. Haddadi , S. Farhangi , F. Blaabjerg . "A reliable three-phase single-stage multiport inverter for grid-connected photovoltaic applications". in IEEE Journal of Emerging and Selected Topics in Power Electronics, 2019. 7 (4): 2384 - 2393,
[23]
P. Sangani , R. Makholia , V. Pagolu , N. K. M , B. P. D. V , D. Barki . "Comparison of different anti-PID techniques for grid-tied isolated solar inverters", in 2021 IEEE 48th Photovoltaic Specialists Conference (PVSC), Fort Lauderdale, FL, USA, 2021. 1987 - 1989,
[24]
Z. Xueguang , W. Li , Y. Xiao , G. Wang , D. Xu . "Analysis and suppression of circulating current caused by carrier phase difference in parallel voltage source inverters with SVPWM". in IEEE Transactions on Power Electronics, 2018. 33 (12): 11007 - 11020,
[25]
B. K. Gupta , K. R. Sekhar , A. I. Gedam . "Balanced per-phase sequential switching to suppress circulating current in grid connected modular solar inverters", in 2019 8th International Conference on Renewable Energy Research and Applications (ICRERA), Brasov, Romania, 2019. 686 - 691,
[26]
B. K. Gupta , K. R. Sekhar , A. I. Gedam . "Solar interfaced series inverter with provision of common DC bus grounding". in IEEE Transactions on Industrial Electronics, 2022. 69 (4): 3656 - 3666,
Appendix
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Year 2024 volume 9 Issue 4
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Cite this Article
BibTeX
Article Info
doi: 10.24295/CPSSTPEA.2024.00020
  • Receive Date：2023-10-10
  • Online Date：2025-07-05
  • Published：2024-12-10
Article Data
Affiliations
History
  • Received：2023-10-10
  • Revised：2024-08-08
  • Accepted：2024-09-18
Funding
Ministry of Electronics and Information Technology(25(2)2021-ESDA)
Science and Engineering Research Board(CRG/2020/002958)
Affiliations
    Indian Institute of Technology Ropar Department of Electrical Engineering Rupnagar 140001 India

Corresponding:

Baibhav Kumar Gupta.
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表12种不同金属材料的力学参数
科
Family		 属数
Number of
genus		 种数
Number of
species		 占总种数比例
Percentage of
total species (%)		 属
Genus		 种数
Number of
species		 占总种数比例
Percentage of total
species (%)
鹅膏菌科Amanitaceae 2 11 5.26 鹅膏菌属 Amanita 10 4.78
小菇科 Mycenaceae 2 12 5.74 丝盖伞属 Inocybe 5 2.39
多孔菌科 Polyporaceae 8 14 6.70 蜡蘑属 Laccaria 5 2.39
红菇科 Russulaceae 3 23 11.00 小皮伞属 Marasmius 6 2.87
小菇属 Mycena 11 5.26
光柄菇属 Pluteus 5 2.39
红菇属 Russula 17 8.13
栓菌属 Trametes 5 2.39
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