Home Journals Articles Updates About
CN
image
收藏切换
A Novel Topology and Modulation Strategy for the High-Gain Hybrid Active Neutral-Point-Clamped Three-Level Inverter
收藏切换
PDF
Chuanjing HOU1, 2, Desheng JIA1, 2, Changwei QIN1, 2, Xiaoyan LI1, 2
CPSS Transactions on Power Electronics and Applications | 2025, 10(1) : 44 - 54
Less
收藏切换
CPSS Transactions on Power Electronics and Applications | 2025, 10(1): 44-54
• Original articles •
A Novel Topology and Modulation Strategy for the High-Gain Hybrid Active Neutral-Point-Clamped Three-Level Inverter
Full
Chuanjing HOU1, 2, Desheng JIA1, 2, Changwei QIN1, 2, Xiaoyan LI1, 2
Affiliations
  • 1 Shandong Jianzhu University School of Information and Electrical Engineering Jinan 250101 China
  • 2 Shandong Key Laboratory of Smart Buildings and Energy Efficiency Jinan 250101 China

    • Chuanjing Hou received the Ph.D. degree in control science and engineering from Shanghai Jiao Tong University, Shanghai, China, in 2018. He is currently an Associate Professor with the School of Information and Electrical Engineering, Shandong Jianzhu University. His research interests include high-gain multilevel inverter.

    Desheng Jia received the B.S. degree in electrical engineering and automation from Weifang University of Science and Technology University, Weifang, China, in 2022. He is currently pursuing the M.S. degree in control engineering with Shandong Jianzhu University, Jinan, China. His current research interests include SiC&Si hybrid ANPC three-level inverter.

    Changwei Qin received the Ph.D. degree in electrical engineering from Shandong University, Jinan, China, in 2019. In 2020, he joined Shandong Jianzhu University, where he is currently an Associate Professor. His current research interests include control of multi-level converters and impedance source converters.

    Xiaoyan Li received the Ph.D. degree in electrical engineering from Shandong University, Jinan, China, in 2020. From 2021 to 2023, she was a Postdoctoral Research Fellow with Shandong University, Jinan, China. In 2023, she joined Shandong Jianzhu University, where she is currently an Associate Professor. Her current research interests include control of multi-level converters and power quality control.

Published: 2025-03-10 doi: 10.24295/CPSSTPEA.2024.00028
Outline
收藏切换

The hybrid active neutralpointclamped (HANPC) threelevel inverter (TLI) has the advantage of high efficiency and low cost due to the partial use of SiC devices. However, the magnitude of AC output voltage cannot exceed that of DC input voltage, which limits its application field. This paper puts forward a novel topology and modulation method of the highgain HANPC TLI. The proposed topology combines the advantages of reduced count of SiC MOSFETs and singlestage boosting ability. To further improve system efficiency, a novel modulation method is designed, in which the SiC MOSFETs and Si IGBTs are operated in high frequency and fundamental frequency, respectively. To realize the function of voltage boosting without affecting the normal ac output voltage, the uppershootthrough (UST) and lowershootthrough (LST) states are inserted within the dwell times of small vectors. Moreover, the neutral point (NP) voltage balance is actively controlled by introducing a distribution factor to regulate duty cycle of redundant small vectors, which improve system reliability. Experimental tests verify the performance of the proposed topology and strategy.

Hybrid active neutral-point-clamped (HANPC)  /  neutral point (NP) voltage  /  quasi-Z-source  /  silicon carbide (SiC).
Chuanjing HOU, Desheng JIA, Changwei QIN, Xiaoyan LI. A Novel Topology and Modulation Strategy for the High-Gain Hybrid Active Neutral-Point-Clamped Three-Level Inverter[J]. CPSS Transactions on Power Electronics and Applications, 2025 , 10 (1) : 44 -54 . DOI: 10.24295/CPSSTPEA.2024.00028
Full Text
Less
I. INTRODUCTION
Less
THE three-level inverter (TLI) has the distinct superiorities of reduced voltage stress of semiconductors, high efficiency, and small instantaneous rate of voltage change $\left({\mathrm{d}v/\mathrm{d}t}\right) \left\lbrack 1\right\rbrack$, [2]. It has been extensively employed in varieties of industrial fields, such as photovoltaic power system, electric vehicles, and electric drive, etc [3]-[5].
Among a variety of multilevel inverters, the neutral-point-clamped (NPC) TLI is one typical topology that is utilized in medium and high voltage applications [6],[7]. However, it has the drawback of an uneven loss distribution among the semiconductors. To cope with this issue, the active NPC (ANPC) topology and its corresponding modulation scheme have been developed [8]-[10]. In the ANPC topology, the clamping diodes is replaced with the Si IGBTs.
In industrial applications, the efficiency as well as the power density is expected to be as high as possible, which means that the achievement of lower hardware cost [11]. Recently, with the development of SiC devices, a full-SiC active neutral-point-clamped (ANPC) TLI is proposed to enhance efficiency and power density [12]. Moreover, since SiC devices have lower switching loss, full-SiC ANPC TLI can be operated in higher switching frequency, and the filter size is reduced consequently. However, SiC devices are about four times as expensive as Si IGBTs, which greatly increases the system cost.
The Si/SiC hybrid converters is an alternative approach to achieve the tradeoff between performance and cost [13]. The SiC MOSFETs are used to replace part of Si IGBTs to construct hybrid active neutral-point-clamped (HANPC) topology [14]. Additionally, switching actions are shifted from Si IGBTs to SiC MOSFETs by utilizing the inherent redundancy states on each phase. Only the Si IGBTs are operated in fundamental frequency, which mitigates switching loss and improves system efficiency. However, similar to the conventional dc/ac converter, the HANPC TLI faces the problem that the amplitude of ac output voltage cannot exceed that of dc input voltage, which brings about limitations in practical applications. To solve this problem, a dc/dc boost circuit is usually configured to attain the desired voltage level. However, this configuration adds the control complexity [15],[16].
Fortunately, the emergence of quasi-Z-sources allows single-stage inverters to have voltage buck-boost capability, which can extend the output voltage range [17],[18]. Comparing with the two-stage solution, the power conversion stage is reduced, and dead-time of power devices is avoided, which effectively improves system reliability. Among single-stage inverters, the quasi-Z-source inverter maintains the superiority of continuous current and have been widely used in practical applications [19]. Recently, a reduced switch count (RSC) quasi-Z-source TLI has been proposed, which reduces the system cost and increases the output voltage range [20]. However, due to inherent defects of the RSC TLI topology, the medium vector cannot be obtained, and at the same time, the switching state directly jump from [P] to [N] (or [N] to [P]) in one sampling period when designing the switching sequence, adding additional switching losses.
As the above analyses reveal, to further improve the performance and reduce system cost of the inverter, this paper presents a novel high-gain HANPC TLI, which consists of a quasi-Z-source network and a HANPC TLI. The novel high-gain HANPC TLI combines the advantages of quasi-Z-source and HANPC inverter [21]. To realize the normal operation and further improve efficiency of the proposed topology, a novel modulation strategy is also presented.
The major novelties of this paper include the following 4 points:
(1) In the proposed high-gain HANPC TLI, only one-third of the total power devices are SiC MOSFETs, and rest power devices are still Si IGBTs, which greatly reduces the system cost. Due to the combination with a quasi-Z-source, the adverse effect of dead time to the output waveform is avoided.
(2) The proposed novel modulation strategy is composed by low-frequency module and high-frequency module, which are used to drive the Si IGBTs and SiC MOSFETs, respectively. Using the novel modulation strategy, the power losses are further decreased, and system performance is also improved.
(3) The dc voltage boosting operation is realized by inserting an upper-shoot-through (UST), abbreviated as [U] and a lower-shoot-through (LST), abbreviated as [L] in the dwell times of small vectors, which broadens the output voltage range and extents topology application field.
(4) A distribution factor is presented to regulate dwell times of redundant small vectors, which realizes the active control of neutral point (NP) voltage and improves system reliability consequently.
II. FUNDAMENTALS OF PROPOSED HIGH-GAIN HANPC TLI
Less
In this section, a detailed descriptions of the novel high-gain HANPC TLI topology are presented, which include topology structure and operational principle.
Fig. 1 shows the structure of circuit for high-gain HANPC TLI, which consists of the dc power source, quasi-Z-source network, HANPC TLI, and load. The HANPC TLI comprises four Si IGBTs switches $\left({{\mathrm{S}}_{x1},{\mathrm{\;S}}_{x2},{\mathrm{\;S}}_{x3}\text{, and}{\mathrm{\;S}}_{x4}}\right)$ and two SiC MOS-FETs switches $\left({\mathrm{Q}}_{x1}\right.$ and $\left. {\mathrm{Q}}_{x2}\right) \left({x = \mathrm{a},\mathrm{b},\mathrm{c}}\right)$ in each phase. The quasi-Z-source network is deployed between the dc source and HANPC TLI. The dc power source voltage and input voltage of the HANPC TLI are indicated to ${V}_{\text{in }}$ and ${V}_{\mathrm{{dc}}}$, respectively.
All the switching states corresponding output states and voltage levels of the high-gain HANPC TLI are summed up in Table I, where ” 1 ” and ” 0 ” represent the on and off states of semiconductor devices, respectively. In this way, six different output states can be generated in the proposed high-gain HAN-PC TLI. Notably, the NPC TLI merely having three output states [P], [N], and [O], the proposed topology contains six output states [P], [N], [O+], [O-], [U] and [L]. With the above characteristics, the high-gain HANPC TLI has the potential to boost input dc voltage and equalize the distribution of switching losses.
As we all know that the switching losses of SiC MOSFET device is about one-third to one-fifth of that of Si IGBTs device with the same power rating [22]. Nevertheless, the SiC MOSFETs is approximately four times more expensive than Si IGBTs. In the proposed topology, only a third of the semiconductors are SiC MOSFETs, and rest of power switches are Si IGBTs, which reduce the system cost, consequently.
By designing a reasonable modulation strategy, the six SiC MOSFETs can operate in high-frequency mode and the twelve Si IGBTs can operate in fundamental frequency mode, which further reduces switching losses, and thus improves system efficiency [23]-[25]. To realize dc input voltage boosting and maintain the reduced switching losses, a new modulation method is presented in Section IV.
III. Comparative Summary and Design Guidelines
Less
A. Comparison of the High-Gain HANPC TLI With Other TLI Based on Impedance Sources or SiC Devices
The detailed comparisons of the high-gain HANPC TLI and the existing TLI based on impedance sources or SiC devices have been conducted, which including Z-source neutral-point clamped (NPC) TLI with two separated impedance networks (ZS NPC3L with 2-LC) [26], Z-source three-level T-type inverter (ZS 3LT2I) [27], quasi-Z-source three-level T-type inverter (QZS 3LT2I) [28] and full-SiC active neutral-point-clamped TLI (Full-SiC ANPC TLI) [12].
Table II summarizes the detailed comparisons of different TLI. Compared with the conventional Z-source inverter, the proposed high-gain HANPC TLI draws a continuous input current, since the inductor is directly connected to the DC power source. When compared to the traditional quasi-Z-source T-type and NPC TLI, the high-gain HANPC TLI boasts higher power density and efficiency. In contrast to the full-SiC ANPC TLI, the proposed high-gain HANPC TLI topology employs only six SiC devices, the system cost can be reduced accordingly. The hybrid ANPC requires much fewer SiC MOSFETs than a full-SiC ANPC inverter while providing a comparable power density [29].
B. Design Criterion and Formulations for Passive Components in the High-Gain HANPC TLI
The design criterion and formulations for passive components in the quasi-Z-source network are elaborated as follows.
Since the high-gain HANPC TLI belongs to one kind of quasi-Z-source inverter in essence, the passive components in the quasi-Z-source network are designed by referring the methodology presented in [20], [30].
The inductances are calculated by
$ {L}_{1} = {L}_{2} = {L}_{3} = {L}_{4} \geq \frac{{V}_{\text{in }}^{2} \cdot \left({1 - {d}_{\mathrm{f}}}\right) \cdot {d}_{\mathrm{f}}}{2 \cdot {P}_{\text{out }} \cdot {f}_{\mathrm{{sw}}} \cdot {k}_{L} \cdot \left({1 - 2{d}_{\mathrm{f}}}\right) } $
where ${V}_{\mathrm{{in}}},{d}_{\mathrm{f}},{P}_{\mathrm{{out}}},{f}_{\mathrm{{sw}}}$, and ${k}_{L}$ are the dc input voltage, shoot-through duty cycle, output power of the inverter, switching frequency, and the current ripple factor of inductors, respectively.
The capacitances are formulated by
$ {C}_{1} = {C}_{4} \geq \frac{2 \cdot {P}_{\text{out }}}{{V}_{\text{in }}^{2} \cdot {k}_{{C1},4} \cdot {f}_{\text{sw }}} \cdot \left({1 - 2{d}_{\mathrm{f}}}\right) $
$ {C}_{2} = {C}_{3} \geq \frac{2 \cdot {P}_{\text{out }}}{{V}_{\text{in }}^{2} \cdot {k}_{{C2},3} \cdot {f}_{\mathrm{{sw}}}} \cdot \frac{1 - 2{d}_{\mathrm{f}}}{1 - {d}_{\mathrm{f}}} \cdot {d}_{\mathrm{f}} $
where ${k}_{{C1},4}$ is the voltage ripple factor of capacitors C1 and C4 , while ${k}_{{C2},3}$ is the voltage ripple factor of capacitors C2 and C3 .
In the designed high-gain HANPC TLI, the current ripple factor of inductors $\left({k}_{L}\right)$ is selected as ${0.6}.{k}_{C1.4}$ is selected as 0.0009, while ${k}_{{C2},3}$ are selected as 0.0007. The maximum dc input voltage is ${400}\mathrm{\;V}$, the maximum output power is $4\mathrm{\;{kW}}$, and the switching frequency is ${10}\mathrm{{kHz}}$.
Based on the above parameters, the values of capacitors and inductors can be calculated. The inductance of L1, L2, L3, and L4 is selected as $1\mathrm{{mH}}$, the capacitance of C1 and C4 is chosen as ${2350\mu }\mathrm{F}$, and the capacitance of C2 and C3 is selected as 1410 $\mu \mathrm{F}$. In the experimental verification, it is noted that C1 and C4 are built by connecting five 470 µF/450 V electrolytic capacitors in parallel, while C2 and C3 are built by connecting three ${470\mu }\mathrm{F}/{450}\mathrm{\;V}$ electrolytic capacitors in parallel. For the diodes in the quasi-Z-source network, the fast recovery epitaxial diode (FRED) DSEI60-06A is selected.
IV. Proposed Novel Modulation Scheme
Less
The proposed strategy consists of four steps. Firstly, according to the sector and region of the reference voltage vector $\left({V}_{\text{ref }}\right)$, basic vectors are selected, and the corresponding duty cycles are calculated for synthesizing the Vref. For the second part, the capacitor voltages ${V}_{C2}$ and ${V}_{C3}$ are actively controlled in balance by introducing the distribution factor $\left(\eta \right)$. For the third part, depending on the $\eta$ and the set shoot-through duty cycle $\left({d}_{\mathrm{f}}\right)$, the durations of small vectors are adjusted, which implements the boost function and maintains the normal output waveforms. At last, the switching sequences of SiC MOSFETs and Si IGBTs are designed separately, and the hybrid frequency pulse driving signals are generated. The control diagram is given in Fig. 2. For each part, the design process is elaborated below.
A. Basic Vectors Selection and Duty Cycles Calculation
With the different output states of three phases, the space vector diagram (SVD) of high-gain HANPC TLI is illustrated in Fig. 3, which includes 27 non-shoot-through basic voltage vectors. It should be noted that since quasi-Z-source network is included in the proposed high-gain HANPC TLI, the shoot-through vectors consisting of [U] and [L] states can be generated for voltage boosting operation.
According to the values of M and $\theta$ of the Vref, the sector and region number of the Vref location can be determined, where $\theta$ and M are the phase angle and modulation index of Vref, respectively. Only the location of Vref is determined, the basic voltage vectors can be selected consequently.
In each sector, the duration calculation of selected vectors still follows the same principles of conventional three-level space vector modulation (3L-SVM) [31], which is also based on “volt-second balancing” formula. As shown in Fig. 4, when Vref is located in the region 5 of sector I (abbreviated as I-5), the “nearest three vectors” (NTV) scheme is utilized. Four basic voltage vectors are chosen according to the NTV principle, i.e., [ONN], [PNN], [PON], [POO], and the duty cycles are noted as ${d}_{1},{d}_{2},{d}_{3}$ and ${d}_{4}$, respectively. The formula that calculates the duty cycles are given in (4):
$ \left\{ \begin{array}{l} {V}_{\text{ref }}\cos \theta = \frac{{V}_{\text{in }}}{3} \cdot {d}_{1} + \frac{2{V}_{\text{in }}}{3} \cdot {d}_{2} + \frac{\sqrt{3}{V}_{\text{in }}}{3} \cdot \frac{\sqrt{3}}{2} \cdot {d}_{3} + \frac{{V}_{\text{in }}}{3} \cdot {d}_{4} \\ {V}_{\text{ref }}\sin \theta = \frac{\sqrt{3}{V}_{\text{in }}}{3} \cdot \frac{1}{2} \cdot {d}_{3} \\ {d}_{1} + {d}_{2} + {d}_{3} + {d}_{4} = 1 \\ {d}_{1} = {d}_{4} \end{array}\right. $
The duty cycles of ${d}_{1},{d}_{2},{d}_{3}$ and ${d}_{4}$ can be calculated as:
$ \left\{ \begin{array}{l} {d}_{1} = 1 - \frac{\sqrt{3}{V}_{\text{ref }}}{{V}_{\text{in }}}\sin \left({\frac{\pi }{3} + \theta }\right) \\ {d}_{2} = \frac{2 \cdot \sqrt{3}{V}_{\text{ref }}}{{V}_{\text{in }}}\sin \left({\frac{\pi }{3} - \theta }\right) - 1 \\ {d}_{3} = \frac{2 \cdot \sqrt{3}{V}_{\text{ref }}}{{V}_{\text{in }}}\sin \theta \\ {d}_{4} = 1 - \frac{\sqrt{3}{V}_{\text{ref }}}{{V}_{\text{out }}}\sin \left({\frac{\pi }{3} + \theta }\right) \end{array}\right. $
Generally, following the principle of conventional 3L-SVM, the switching sequence is designed to [ONN]-[PNN]-[PON]- [POO]-[PON]-[PNN]-[ONN]. It should be noted that the [O] state contains two states, [O+] and [O-], which are determined by its neighboring states, [O+] states are only adjacent to [P] and [U] states, [O-] states are only adjacent to [N] and [L]. Based on the above principles, the least switching times and switching losses are guaranteed, and the actual switching sequence is designed as [O+NN]-[PNN]-[PO-N]-[PO-O-]-[PO-N]-[PNN]-[O+NN].
B. NP Voltage Balance Active Control
A distribution factor is introduced to regulate duty cycles of redundant small vectors, thus realizing the NP voltage balance.
First, the voltages across C2 and C3 are sampled, and noted as ${V}_{C2}$ and ${V}_{C3}$, respectively. Next, the difference between ${V}_{C2}$ and ${V}_{C3}$ is adjusted by a proportional controller, and $\eta$ is obtained as:
$ \eta = p \cdot \left({{V}_{\mathrm{C}2} - {V}_{\mathrm{C}3}}\right) $
where $p$ is the proportional control factor.
Lastly, the limiting of $\eta$ is required to prevent voltage distortion, the formula is given in (7).
$ - \left({1 - m - {d}_{\mathrm{f}}}\right) < \eta < 1 - m - {d}_{\mathrm{f}} $
C. Shoot-Through States Injection and Duty Cycles Update
In the case of the proposed method, the utilization of [U] and [L] states enable the implementation of boost function. [U] and [L] are injected within the dwell time of small vectors. Additionally, the duration of small vectors is adjusted through modification of the NP voltage distribution factor.
Considering the addition of NP voltage balance control scheme and the injection of [U] and [L] states, the duty cycles of basic voltage vectors are revised as:
$ \left\{ \begin{array}{l} {d}_{1}^{\prime } = {d}_{1} - {d}_{\mathrm{f}} - \eta \\ {d}_{2}^{\prime } = {d}_{2} \\ {d}_{3}^{\prime } = {d}_{3} \\ {d}_{4}^{\prime } = {d}_{4} - {d}_{\mathrm{f}} + \eta \end{array}\right. $
The dwell times of basic voltage vectors can be calculated as:
$ \left\{ \begin{array}{l} {T}_{ * }^{\prime } = {d}_{ * }^{\prime } \cdot {T}_{\mathrm{s}} \\ {T}_{\mathrm{{UST}}} = {T}_{\mathrm{{LST}}} = {d}_{\mathrm{f}} \cdot \frac{{T}_{\mathrm{s}}}{2} \end{array}\right. $
where * represents the segment of the switch sequence $(1,2,3$ and 4) and ${T}_{\mathrm{s}}$ is the sampling period.
D. Switching Sequences Arrangement and Drive Signals Generation
The design of switching sequences should follow certain principles, which ensure the quality of the output waveforms and as few switching times as possible.
The [U] and [L] states are inserted, and the boost function is implemented. Simultaneously, the dwell times of the redundant small vectors are adjusted for achieving NP voltage balance. As the above analyses demonstrate, eleven segment switching sequences are arranged, the actual switching sequence (I-5) is designed as $\left\lbrack {{\mathrm{O}}_{ + }\mathrm{{NN}}}\right\rbrack - \left\lbrack \mathrm{{UNN}}\right\rbrack - \left\lbrack \mathrm{{PNN}}\right\rbrack - \left\lbrack \mathrm{{PO}\_ N}\right\rbrack - \left\lbrack \mathrm{{PO}\_ L}\right\rbrack - \left\lbrack {{\mathrm{{PO}}}_{ - }\mathrm{O}}\right\rbrack -$ [PO_L]-[PO_N]-[PNN]-[UNN]-[O+NN].
When the Vref is located in I-5, the arranged switching sequence and the switching state of power devices are drawn in Fig. 5. In one sampling period, the output states of each phase change between [P], [O+] and [U] states or between [N], [O-] and [L] states, and the switching states of Si IGBTs are always turn-on or turn-off. For example, for phase A, the output states change between [P], [O+] and [U] states. The Si $\mathrm{{IGBTs}}$ of ${\mathrm{S}}_{\mathrm{{al}}}$, ${\mathrm{S}}_{\mathrm{a}3}$ are always turn-on, and ${\mathrm{S}}_{\mathrm{a}2},{\mathrm{S}}_{\mathrm{a}4}$ are always turn-off in one sampling period. While the switching states of SiC MOSFETs switch turn-on and switch turn-off one time in one sampling period. Thus, the working frequency of SiC MOSFETs is equal to sampling frequency, which is defined as high frequency modulation. Considering the symmetry of SVD, the rules of switching sequences in other sectors are similar to above analysis and will not repeat here.
For phase B and phase C, output states have similar changing law. Table III summarizes the output states of each phase in one fundamental period. Therefore, the working frequency of all Si IGBTs in the proposed high-gain HANPC TLI is equal to fundamental frequency, which is defined as fundamental frequency modulation.
V. Simulation Results
Less
The effectiveness of the proposed topology and scheme is demonstrated by adopting MATLAB software. Since the high-gain HANPC TLI is essentially a type of quasi-Z-source TLI, the design of passive components in quasi-Z-source is referred to [20] and [30]. The parameters for both simulation and experimental tests are given in Table IV. The high-gain HANPC TLI can be operated in non-boost and boost modes as required, in non-boost mode, the shoot-through state is not required.
To verify the effect of different gains on the total harmonic distortion (THD) of current at the same power, four different operation conditions are compared and analyzed: (a) $m = {0.8},{d}_{\mathrm{f}} = 0$, (b) $m = {0.7},{d}_{\mathrm{f}} = {0.05},\left(\mathrm{c}\right) m = {0.8},{d}_{\mathrm{f}} = {0.1},\left(\mathrm{d}\right) m = {0.7},{d}_{\mathrm{f}} = {0.15}$.
Fig. 6 displays the simulated results in steady state, and the total harmonic distortion of output current (THDi) is also given. The proposed high-gain HANPC TLI belongs to one kind of quasi-Z-source inverter in essence. Due to the injection of the shoot-through state, the input voltage of the HANPC TLI (Vdc) is changed to a pulse waveform, while the normal ac output voltage is not affected [30].
Fig. 6 (a) shows the output waveform in non-boost mode. At this time, the system modulation index(m)and the shoot-through ${d}_{\mathrm{f}}$ are set as 0.8 and 0, respectively. The dc input voltage $\left({V}_{\mathrm{{in}}}\right)$ is set to be 70V, and the dc-link voltage (Vdc) is equal to the dc input voltage. The voltages of dc-link capacitors C2 and C3 are balanced at 35V, which is half of the dc-link voltage magnitude. The waveform of line voltage $\left({v}_{\mathrm{{ab}}}\right)$ has five levels, that is, $0, \pm {35}\mathrm{\;V}$, and $\pm {70}\mathrm{\;V}$, which validate the correctness of the designed modulation scheme. Moreover, three-phase output currents $\left({{i}_{\mathrm{a}},{i}_{\mathrm{b}}}\right.$, and $\left. {i}_{\mathrm{c}}\right)$ are symmetrical and sinusoidal.
The simulation results in boost mode are shown in Fig. 6 (b)-(d), respectively. It is clearly observed that the dc-link voltage becomes pulse waveform, whose magnitude is higher than the dc input voltage due to the utilization of shoot-through states. It can be concluded that the voltage boosting capability is realized. Table V summarizes the THD of the current and the output power for various operating conditions. Under the condition of keeping the output power constant, the THD of the current shows an upward trend with the increasing of the through duty cycle. However, the quality of the current waveform can still be well guaranteed.
The gate signals of all power switches in phase A of the inverter are demonstrated in Fig. 7. In one fundamental period, the Si IGBTs ${\mathrm{S}}_{\mathrm{a}1},{\mathrm{\;S}}_{\mathrm{a}2},{\mathrm{\;S}}_{\mathrm{a}3}$, and ${\mathrm{S}}_{\mathrm{a}4}$ only switch once. It is easy to see that the switching action is mainly shifted to SiC devices with better switching loss performance. The Si devices operate solely at the fundamental frequency to minimize switching loss. On the other hand, the drive signals of ${\mathrm{Q}}_{\mathrm{a}1}$ and ${\mathrm{Q}}_{\mathrm{a}2}$ are complementary in the non-boost mode, and in the boost mode, the drive signals of ${\mathrm{Q}}_{\mathrm{a}1}$ and ${\mathrm{Q}}_{\mathrm{a}2}$ exhibit shoot-through time, and a higher shoot-through duty cycle results in an extended shoot-through duration.
The proposed quasi-Z-source inverter should preferably operate under high modulation condition when voltage boosting (output voltage greater than ${V}_{\text{in }}$ and with shoot-through states inserted) is commanded [32]. In order to verify that the system can operate normally under different M, indices M changes from 0.8 to 0.7, and the dynamic output results are shown in Fig. 8. Obviously, the output current is proportionally decreased with the reduction of M in both boost and non-boost modes, while the voltage boosting capacity is not influenced.
To verify the effectiveness of the NP voltage balance control strategy, an extra ${500\Omega }$ resistor is connected in parallel with C2 , Fig. 9 shows the simulated waveforms. Originally, the NP voltage balance control is enabled, ${V}_{C2}$ and ${V}_{C3}$ are balanced. The NP voltage balancing control is manually disabled when the simulation time is ${0.7}\mathrm{\;s}$. Accordingly, ${V}_{C2}$ and ${V}_{C3}$ are separated. In both non-boost and boost modes, the effectiveness of the NP voltage balance control is verified. When the load resistance changes in step, simulated waveforms are depicted in Fig. 10. It is observed that the proposed scheme ensures the stable operation of the high-gain HANPC TLI under both conditions.
Fig. 11 displays the losses of power devices in the high-gain HANPC TLI, which are obtained by adopting MATLAB/ Simulink and PLECS Blockset. According to the symmetrical characteristics of the topology, the loss of ${\mathrm{S}}_{\mathrm{a}1}$ is identical to that of ${\mathrm{S}}_{\mathrm{a}4}$, and similar conclusions can be obtained for other power switches. It is noted that the losses of power switches include those of the body diodes. It is seen that the conduction losses accounts for the majority of the total power loss. Overall, the losses of power devices are relatively equalized.
Under the condition of consistent output power, it is observed that the increase in the ${d}_{\mathrm{f}}$ leads to a slight increase in power loss. Further analysis shows that the switching loss shows a significant upward trend when the output power is increased. Based on the above observations, it is reasonable to infer that the power loss is mainly affected by the output power and also modulated to some extent by the ${d}_{\mathrm{f}}$.
VI. Experimental Results
Less
To validate the performance of the proposed topology and modulation scheme, an experimental test system of the high-gain HANPC TLI is designed, as shown in Fig. 12.
The digital signal processor of the control board is TMS320 F28377D from Texas Instruments. The IGBT IKW50N65EH5 is adopted for power switches ${\mathrm{S}}_{x1} - {\mathrm{S}}_{x4}$, while the MOSFET IM-W65R027M1H is adopted for power switches ${\mathrm{Q}}_{x1} - {\mathrm{Q}}_{x2}$.
Fig. 13 shows the operating waveforms of the high-gain HANPC TLI in non-boost mode. At this time, the M and ${d}_{\mathrm{f}}$ are set as 0.8 and 0, respectively. The capacitor voltages ${V}_{C2}$ and ${V}_{C3}$ are maintained at 35 V, i.e., ${V}_{\mathrm{{in}}}/2$. The line voltage $\left({v}_{\mathrm{{ab}}}\right)$ is five level waveforms, which comprise $0, \pm {35}\mathrm{\;V}$, and $\pm {70}\mathrm{\;V}$. In addition, the load currents $\left({{i}_{\mathrm{a}},{i}_{\mathrm{b}}}\right.$, and $\left. {i}_{\mathrm{c}}\right)$ are symmetrical and sinusoidal, which verified the validity of the proposed modulation method.
As observed from Fig. 13(b), the drive signals of the power switches are consistent with the simulation results. It can be found that the Si IGBTs ${\mathrm{S}}_{x1},{\mathrm{\;S}}_{x2},{\mathrm{\;S}}_{x3}$, and ${\mathrm{S}}_{x4}$ only switch once in one fundamental period. As it can be observed from the enlarged figure, the working frequency of SiC MOSFETs is equivalent to the sampling frequency. Furthermore, ${\mathrm{Q}}_{\mathrm{a}1}$ and ${\mathrm{Q}}_{\mathrm{a}2}$ are complementary signals that exhibit no shoot-through state. While the SiC MOSFETs ${\mathrm{Q}}_{x1}$ and ${\mathrm{Q}}_{x2}$ operate in high frequency switching of ${10}\mathrm{{kHz}}$. In this case, the voltages across capacitors C2 and C3 are about ${35}\mathrm{\;V}$, and the NP voltage balance is guaranteed by the proposed method, as shown in Fig. 13(d).
The spectra of ${v}_{\mathrm{{ab}}}$ and ${i}_{\mathrm{a}}$ are obtained using MATLAB software, which are provided in Fig. 13(e) and (f), respectively. These spectra show that the main components of ${v}_{\mathrm{{ab}}}$ and ${i}_{\mathrm{a}}$ are concentrated at ${50}\mathrm{\;{Hz}}$, switching frequency(10kHz)and multiples of switching frequency.
Fig. 14 displays the experimental waveforms in boost mode, and the ${d}_{\mathrm{f}}$ is set as 0.1. The ${V}_{\mathrm{{dc}}}$ is changed to a pulse waveform. It is noticed that the line voltage and current amplitude have increased. In non-boost mode $\left({m = {0.8},{d}_{\mathrm{f}} = 0}\right)$, the amplitude of the line voltage is about ${64}\mathrm{\;V}$. In addition, the load currents $\left({{i}_{\mathrm{a}},{i}_{\mathrm{b}}}\right.$, and $\left. {i}_{\mathrm{c}}\right)$ are symmetrical and sinusoidal, the amplitude of output current is about ${3.8}\mathrm{\;A}$. In boost mode $\left({m = {0.8},{d}_{\mathrm{f}} = {0.1}}\right)$, the amplitude of the line voltage is increased to about ${80}\mathrm{\;V}$ and the amplitude of output current is increased to about ${4.7}\mathrm{\;A}$. Noteworthy, there is some attenuation of voltage and current as it passes through the transducer and oscilloscope display, but the values of voltage and current increase before and after boosting are in accordance with (10).
$ {V}_{\mathrm{{dc}}} = {V}_{\text{in }}/\left({1 - 2{d}_{\mathrm{f}}}\right) = B{V}_{\text{in }} $
Obviously, the boost function is realized. In boost mode, the driving signal of power switches are shown in Fig. 14(b), the injection of the shoot-through state does not add additional switching action, thereby preventing an increase in switching loss. Furthermore, the boost function is accomplished during the shoot-through time. It is noteworthy that within one sampling period, only one of the three phases has a shoot-through time, and the high frequency drive signals for the remaining two phases are similar to Fig. 13(b). Moreover, the voltages across C2 and C3 are balanced as well, as shown in Fig. 14(d). The spectra of ${v}_{\mathrm{{ab}}}$ and ${i}_{\mathrm{a}}$ are also provided in Fig. 14(e) and (f).
Fig. 15 depicts the experimental waveforms with the variation of the modulation index. Evidently, the magnitude of load current decreases when the modulation index is given as 0.7. Additionally, the excellent output current quality can be guaranteed.
To verify the NP voltage control capability of the proposed method in practical applications, the experimental conditions are configured to be consistent with the simulation conditions. As shown in Fig. 16, the transient waveforms are obtained in non-boost and boost modes. During the operation of the high-gain HANPC TLI, the NP voltage balance control is disabled by a button on the controller. The voltages across C2 and C3 are no longer balanced. The NP voltage imbalance causes current harmonics (specifically reflected in the THD), reduces output power quality, and even damages power switches. Therefore, it is essential to control the NP voltage balance while maintaining high output quality.
In order to more intuitively observe the effect of the NP voltage imbalance on the output current, the data for output current waveforms are stored by adopting the digital storage oscilloscope, and the THD of output current are subsequently obtained by using the MATLAB software. It can be seen that after the NP voltage separation, the current THD increases in both non-boost and boost modes.
Fig. 17 illustrates the dynamic output waveforms with load changes. The experimental results are consistent with the simulation results. With the decrease of load resistance, the output current magnitude is increased. Thus, the proposed method effectively ensures the normal operation under varying load conditions.
VII. CONCLUSION
Less
This paper presents a novel high-gain HANPC TLI topology, which has the advantages of reduced cost and voltage boosting ability. Based on the characterization of the proposed topology, a hybrid frequency modulation scheme for the proposed topology is implemented. First, to achieve the balance of NP voltage and boosting function, a NP voltage distribution factor and shoot-through duty cycles were introduced. In addition, the switching sequences are designed separately, accordingly, the gate drive signals of the power devices are generated. The hybrid frequency modulation is realized by the proposed modulation method, which further reduce the switching losses. In grid-tied photovoltaic (PV) systems, the high-gain HANPC TLI presents an alternative to traditional Si-based inverters. Furthermore, the proposed inverter topology can be applied in motor drives for electric vehicles and power supplies for modern data centers. To summarize, the proposed inverter has a wider voltage application range, regarding the capability to boost operation.
Funding
Less
  • Taishan Scholar Project of Shandong Province(tsqn202312223)
  • Natural Science Foundation of Shandong Province(ZR2024MF039)
  • Development Plan for Youth Innovation Team of Higher Education Institutions in Shandong Province(2023KJ127)
References
Less
[1]
C. Qin , X. Li , C. Hou , C. Su . "A fast-processing implementation method of virtual space vector modulation for the impedance-source three-level inverter", in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 71, no. 7, pp. 3568–3572, Jul. 2024.
[2]
C. Wang , Z. Li , X. Si , H. Xin . "Control of neutral-point voltage in three-phase four-wire three-level NPC inverter based on the disassembly of zero level", in CPSS Transactions on Power Electronics and Applications, vol. 3, no. 3, pp. 213–222, Sept. 2018.
[3]
J. Chen , D. Jiang , Q. Li . "Attenuation of conducted EMI for three-level inverters through PWM", in CPSS Transactions on Power Electronics and Applications, vol. 3, no. 2, pp. 134–145, Jun. 2018.
[4]
T. Liu , A. Chen , C. Qin , J. Chen , X. Li . "Double vector model predictive control to reduce common-mode voltage without weighting factors for three-level inverters", in IEEE Transitions on Industrial Electronics, vol. 67, no. 10, pp. 8980–8990, Oct. 2020
[5]
D. -T. Do , M. -K. Nguyen , T. -H. Quach , V. -T. Tran , F. Blaabjerg , D. M. Vilathgamuwa . "A PWM scheme for a fault-tolerant three-level quasi-switched boost T-type inverter", in IEEE Journal of Emerging and Selected Topics in Power Electronics, vol. 8, no. 3, pp. 3029–3040, Sept.2020.
[6]
F. Chen , W. Qiao , H. Wang , L. Qu . "A simple zero-sequence voltage injection method for carrier-based pulse width modulation of the three-level NPC inverter", in IEEE Journal of Emerging and Selected Topics in Power Electronics, vol. 9, no. 4, pp. 4687–4699, Aug. 2021.
[7]
H.-J. Lee , T.-G. Woo , S. Kim , Y.-D. Yoon . "Improved neutral-point voltage balancing control with time delay compensation and antiwindup loop for a three-level NPC inverter", in IEEE Transactions on Industry Applications, vol. 57, no. 5, pp. 4970–4980, Sept.-Oct. 2021.
[8]
T. Bruckner S. Bernet . "Loss balancing in three-level voltage source inverters applying active NPC switches,in 2001 IEEE 32nd Annual Power Electronics Specialists Conference, Vancouver, BC, Canada, 2001, vol. 2, pp. 1135–1140.
[9]
L. Ma , T. Kerekes , P. Rodriguez , X. Jin , R. Teodorescu , M. Liserre . "A new PWM strategy for grid-connected half-bridge active NPC converters with losses distribution balancing mechanism", in IEEE Transactions on Power Electronics, vol. 30, no. 9, pp. 5331–5340, Sept. 2015.
[10]
Y. Jiao F. C. Lee . "New modulation scheme for three-level active neutral-point-clamped converter with loss and stress reduction", in IEEE Transactions on Industrial Electronics, vol. 62, no. 9, pp. 5468–5479,Sept. 2015.
[11]
L. Zhang , X. Lou , C. Li , F. Wu , Y. Gu , G. Chen , D. Xu . "Evaluation of different Si/SiC hybrid three-level active NPC inverters for high power density", in IEEE Transactions on Power Electronics, vol. 35, no. 8, pp.8224–8236, Aug. 2020.
[12]
D. Barater , C. Concari , G. Buticchi , E. Gurpinar , D. De , A. Castellazzi . "Performance evaluation of a three-level ANPC photovoltaic grid connected inverter with 650-V SiC devices and optimized PWM", in IEEE Transactions on Industry Applications, vol. 52, no. 3, pp. 2475–2485, May-Jun. 2016.
[13]
C. Li , R. Lu , C. Li , W. Li , X. Gu , Y. Fang , H. Ma , X. He . "Space vector modulation for SiC and Si hybrid ANPC converter in medium-voltage high-speed drive system", in IEEE Transactions on Power Electronics, vol. 35, no. 4, pp. 3390–3401, Apr. 2020.
[14]
Y. Zhou , Y. Zhang , P. Du , H. Yang . "Research and application of hybrid ANPC control strategy,in 2022 IEEE 5th International Electrical and Energy Conference (CIEEC), Nanjing, China, 2022. pp.4645-4649.
[15]
D. Zhang , J. He , D. Pan . "A megawatt-scale medium-voltage high efficiency high power density 'SiC+Si' hybrid three-level ANPC inverter for aircraft hybrid-electric propulsion systems", in IEEE Transactions on Industry Applications, vol. 55, no. 6, pp. 5971–5980, Nov.-Dec. 2019.
[16]
Y. Jiang , X. Li , C. Qin , X. Xing , Z. Chen . "Improved particle swarm optimization based selective harmonic elimination and neutral point balance control for three-level inverter in low-voltage ride-through operation", in IEEE Transactions on Industrial Informatics, vol. 18, no. 1, pp.642–652, Jan. 2022.
[17]
F. Z. Peng . "Z-source inverter", in IEEE Transactions on Industry Applications, vol. 39, no. 2, pp. 504–510, Mar.-Apr. 2003.
[18]
X. Guo , Y. Yang , R. He , B. Wang , F. Blaabjerg . "Transformerless Z-source four-leg PV inverter with leakage current reduction", in IEEE Transactions on Power Electronics, vol. 34, no. 5, pp. 4343–4352, May 2019.
[19]
N. Noroozi , M. R. Zolghadri . "Three-phase quasi-Z-source inverter with constant common-mode voltage for photovoltaic application", in IEEE Transitions on Industrial Electronics, vol. 65, no. 6,pp. 4790–4798, Jun. 2018.
[20]
X. Li , C. Qin Z. Chu . "Novel space vector modulation method for the quasi-Z-source asymmetrical three-level inverter", in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 71, no.1, pp. 281–285, Jan. 2024.
[21]
X. Li , C. Qin , Z. Chu J. Fang . "A novel modulation scheme for simultaneous common-mode voltage reduction and neutral-point voltage balance in the reduced switch count quasi-Z-source three-level inverter", in IEEE Transactions on Power Electronics, vol. 38, no. 10, pp. 12035–12047, Oct. 2023.
[22]
Q. Guan , C. Li , Y. Zhang , W. Shuai , D. Xu . "An extreme high efficient three-level active neutral-point-clamped converter comprising SiC &amp; Si hybrid power stage", in IEEE Transactions on Power Electronics, vol. 33, no. 10, pp. 8341–8352, Oct. 2018.
[23]
D. Zhang , J. He , S. Madhusoodhanan . "Three-level two-stage decoupled active NPC converter with Si IGBT and SiC MOSFET", in IEEE Transactions on Industry Applications, vol. 54, no. 6, pp.6169–6178, Nov.-Dec. 2018.
[24]
J. He , D. Zhang , D. Pan . "An improved PWM strategy for SiC + Si three-level active neutral point clamped converter in high-power high frequency applications,in 2018 IEEE Energy Conversion Congress and Exposition (ECCE), Portland, OR, USA, 2018.
[25]
S. S. Hakami , L. M. Halabi , K. -B. Lee . "Dual-carrier-based PWM method for DC-link capacitor lifetime extension in three-level hybrid ANPC inverters", in IEEE Transitions on Industrial Electronics, vol. 70, no. 4, pp. 3303–3314, Apr. 2023.
[26]
P. C. Loh , F. Gao , F. Blaabjerg , S. Y. C. Feng , K. N. J. Soon . "Pulse-width-modulated Z-source neutral-point-clamped inverter", in IEEE Transactions on Industry Applications, vol. 43, no. 5, pp.1295–1308, Sep./Oct. 2007.
[27]
P. C. Loh , S. W. Lim , F. Gao , F. Blaabjerg . "Three-level Z-source inverters using a single LC impedance network", in IEEE Transactions on Power Electronics, vol. 22, no. 2, pp. 706–711, Mar. 2007.
[28]
C. Qin , C. Zhang , X. Xing , X. Li , A. Chen , G. Zhang . "Simultaneous common-mode voltage reduction and neutral-point voltage balance scheme for the quasi-Z-source three-level T-type inverter", in IEEE Transitions on Industrial Electronics, vol. 67, no. 3, pp.1956–1967, Mar. 2020.
[29]
S.-W. An , S. -M. Kim K. -B. Lee . "Capacitor lifetime extension in a hybrid active neutral-point-clamped inverter with reduction of DC-link ripple current and common-mode voltage", in IEEE Access, vol. 9, pp. 40336–40348, 2021.
[30]
C. Qin , X. Xing Y. Jiang . "Topology and space vector modulation method for the reduced switch count quasi-Z-source three-level inverter", in IEEE Transactions on Industrial Electronics, vol. 70,no. 5, pp. 4332–4344, May 2023.
[31]
B. Wu . "High-Power Converters and AC Drives, Hoboken, NJ, USA : Wiley, 2006.
[32]
P. C. Loh , F. Gao , F. Blaabjerg , S. Y. C. Feng K. N. J. Soon . "Pulse-width modulated Z-source neutral-point-clamped inverter", in IEEE Transactions on Industry Applications, vol. 43, no. 5, pp.1295–1308, Sept.-Oct. 2007.
Appendix
Less
Year 2025 volume 10 Issue 1
PDF
397
221
Cite this Article
BibTeX
Article Info
doi: 10.24295/CPSSTPEA.2024.00028
  • Receive Date：2024-08-30
  • Online Date：2025-07-05
  • Published：2025-03-10
Article Data
Affiliations
History
  • Received：2024-08-30
  • Revised：2024-11-15
  • Accepted：2024-12-07
Funding
Taishan Scholar Project of Shandong Province(tsqn202312223)
Natural Science Foundation of Shandong Province(ZR2024MF039)
Development Plan for Youth Innovation Team of Higher Education Institutions in Shandong Province(2023KJ127)
Affiliations
    1 Shandong Jianzhu University School of Information and Electrical Engineering Jinan 250101 China
    2 Shandong Key Laboratory of Smart Buildings and Energy Efficiency Jinan 250101 China

Corresponding:

Changwei Qin
Xiaoyan Li.
References
Share
https://castjournals.cast.org.cn/joweb/dldzjs/EN/10.24295/CPSSTPEA.2024.00028
Share to
QR

Scan QR to access full text

Cite this article
BibTeX
Citations
表12种不同金属材料的力学参数
科
Family		 属数
Number of
genus		 种数
Number of
species		 占总种数比例
Percentage of
total species (%)		 属
Genus		 种数
Number of
species		 占总种数比例
Percentage of total
species (%)
鹅膏菌科Amanitaceae 2 11 5.26 鹅膏菌属 Amanita 10 4.78
小菇科 Mycenaceae 2 12 5.74 丝盖伞属 Inocybe 5 2.39
多孔菌科 Polyporaceae 8 14 6.70 蜡蘑属 Laccaria 5 2.39
红菇科 Russulaceae 3 23 11.00 小皮伞属 Marasmius 6 2.87
小菇属 Mycena 11 5.26
光柄菇属 Pluteus 5 2.39
红菇属 Russula 17 8.13
栓菌属 Trametes 5 2.39
关闭全屏
  • BibTeX
  • EndNote
  • RefWorks
  • TxT
Links
Articles
Latest Articles
Most Read
Collections
Updates
Events
News
Multimedia
About
About Us
Contact
No. 86 Xueyuan South Road, Haidian District, Beijing
100081
010-62199257
qkjq@cast.org.cn

Copyright © 2025 China Association for Science and Technology. All rights reserved. For all open access content, the relevant licensing terms apply.
Sponsored by the Office of the Leading Group for Cybersecurity and Informatization of CAST, and supported by Science and Technology Review Publishing House