Home Journals Articles Updates About
CN
image
收藏切换
Graph Theory-Based Sneak Circuit Time-Domain Analysis and Trigger of CLLC Resonant Converter With Parasitic Parameters
收藏切换
PDF
Chengsong WEI1, Xiaoquan ZHU1, Ke JIN1, Yue WU2
CPSS Transactions on Power Electronics and Applications | 2025, 10(1) : 55 - 65
Less
收藏切换
CPSS Transactions on Power Electronics and Applications | 2025, 10(1): 55-65
• Original articles •
Graph Theory-Based Sneak Circuit Time-Domain Analysis and Trigger of CLLC Resonant Converter With Parasitic Parameters
Full
Chengsong WEI1, Xiaoquan ZHU1, Ke JIN1, Yue WU2
Affiliations
  • 1 Nanjing University of Aeronautics and Astronautics College of Automation Engineering Nanjing 210016 China
  • 2 Electric Power Research Institute of China Southern Power Grid State Key Laboratory of HVDC Guangzhou 510640 China

    • Chengsong Wei was born in Hebei, China, in 2001. He received the B.S. degree in electrical engineering from Hebei University of Technology, China, in 2023. He is working toward the M.S. degree in power electronics from Nanjing University of Aeronautics and Astronautics (NUAA), Nanjing, China. His current research interests include power electronics topologies and renewable energy power generation systems.

    Xiaoquan Zhu received the Ph.D. degree in power electronics at the School of Electric Power Engineering, South China University of Technology, Guangzhou, China, in 2019. He is currently a Lecturer with the College of Automation Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing, China. His current research interests include renewable energy power generation systems and power electronic converters.

    Ke Jin received the Ph.D. degrees in electrical engineering from Nanjing University of Aeronautics and Astronautics in 2006. From 2007 to 2008, he was a Postdoctoral Researcher with Center for Power Electronics Systems, Virginia Polytechnic Institute and State University. He is currently a Professor with College of Automation Engineering, NUAA. His main research interests include high-frequency soft-switching conversion and renewable power systems.

    Yue Wu, was born in Hohhot, China, in 1994. He received the B.S. and M.S. degrees in electrical engineering from Zhejiang University, Hangzhou, in 2017 and 2020. He is currently working for the State Key Laboratory of HVDC (Electric Power Research Institute, China Southern Power Grid), Guangzhou, Guangdong Province, China. His research interests include topology and control of converter, and VSC-HVDC.

Published: 2025-03-10 doi: 10.24295/CPSSTPEA.2025.00003
Outline
收藏切换

The sneak circuits caused by internal parasitic parameters can lead to unexpected phenomena and affect the efficiency and reliability of CLLC resonant converter. Therefore, the characteristic analysis, trigger mechanism and suppression method of CLLC converter sneak circuit based on graph theory are proposed in this paper. The complete current based sneak circuit model and accurate CLLC time domain model are established. Then, the possible sneak circuit phenomena are described in detail to explain their negative effects on the converter operating characteristics, the trigger mechanism of sneak operating modes is put forward, and the suppression conditions are derived. By optimizing the parameter design and modulation parameters of CLLC converter, the unexpected sneak circuits can be avoided. Finally, the correctness of theoretical analysis is verified by experiment results, and the proposed suppression method avoids unnecessary power loss and suppresses the waveform oscillations.

CLLC converter  /  graph theory  /  parasitic parameters  /  sneak circuit  /  time-domain analysis
Chengsong WEI, Xiaoquan ZHU, Ke JIN, Yue WU. Graph Theory-Based Sneak Circuit Time-Domain Analysis and Trigger of CLLC Resonant Converter With Parasitic Parameters[J]. CPSS Transactions on Power Electronics and Applications, 2025 , 10 (1) : 55 -65 . DOI: 10.24295/CPSSTPEA.2025.00003
Full Text
Less
I. INTRODUCTION
Less
WITH the rapid development of electric vehicles (EVs), energy storage systems, and new energy resources, bidirectional dc-dc converters have attracted more and more attention [1],[2]. Bidirectional resonant dc converter has been widely used in these applications as the key device [3]-[5] because the LC resonance process makes both the primary and secondary side currents low-distortion sinusoids, so the switching loss can be kept small while transmitting high power. CLLC converter, as one of the best bidirectional dc converters, is a hot research topic in recent years. However, the dynamic nature of parasitic parameters can lead to waveform oscillations during converter operation [6]. This leads to unexpected sneak circuit phenomena, which will reduce the efficiency and reliability of CLLC converter. Hence, there is a requirement to implement sneak-circuit modeling, analysis and suppression of CLLC converter with parasitic parameters.
Currently, the design of CLLC is mainly based on fundamental harmonic approximation (FHA) analysis method, and the parasitic parameters of switching devices are ignored during the design process, which will lead to unfavorable effects [7]. Thus, time domain analysis method is an effective way to study CLLC resonant converter with parasitic parameters [8]. The current research articles mainly focus on the effect of parasitic parameters on switching performance [9],[10], electromagnetic interference [11],[12], and converter characterization of power converters [13]. Furthermore, considering operation modes with parasitic capacitances, the zero voltage switching (ZVS) behavior is discussed in [14], and the axis and center symmetric (ACS) method was proposed based on currents decomposition to achieve “Sync-ZVS”. Considering the modes that include parasitic capacitances, the ZVS behavior is discussed in references [15],[16]. However, parasitic parameters and its dynamic characteristics can lead to unexpected operating modes and cause nonlinear behavior of the components, such as oscillations in voltage and current, which are detrimental to the converter operating modes but are rarely discussed in existing work.
To further distinguish the difference between sneak and normal operation modes, the sneak circuit analysis method was proposed in [17]. Sneak circuit analysis has two steps: one is sneak path analysis, which identifies the sneak current paths appearing in the converter. And the other is sneak mode analysis, which predicts sneak circuit phenomena [18]. For the sneak path analysis, the existing methods include grid combination analysis [19] and graph-theoretic analysis [20],[21]. However, there is no literature on the sneak operating modes analysis of CLLC resonant converters. Therefore, it is necessary to analyze the sneak circuit phenomena of CLLC converter and build its complete time domain model to get the trigger conditions of the unexpected sneak circuit.
For sneak mode analysis, the existing research articles mainly focus on conventional pulse width modulation (PWM) dc-dc converters such as boost [22] and flyback converters [23]. They all have discontinuous conduction modes, so there are current discontinuity intervals in these PWM dc converters. For the CLLC resonant converter, it also has current discontinuity intervals due to uncontrolled parasitic diodes on the secondary side, while other discontinuity intervals still exist. In the previous analysis, CLLC converter was considered to stop operating during discontinuous current intervals [24]. However, when parasitic elements are considered, currents flow inside the parasitic elements [25] and present sneak operating modes, which will severely affect the converter operating features, such as unstable output characteristics, lower efficiency and higher switching stress [26]. Nevertheless, there are few studies on the sneak circuits analysis when considering the dynamic characteristics of parasitic capacitance in CLLC converter. Therefore, it is necessary to enhance the mechanism analysis of sneak circuits and provide a comprehensive summary of the possible sneak circuit phenomena in CLLC converter.
The trigger mechanism is a prerequisite for suppressing the sneak circuit phenomenon without changing the topology structure. There are four main types of trigger mechanisms and suppression methods: (1) Parameter design: Avoid the appearance of sneak circuits through reasonable parameter design, so that the converter works in the normal operating mode. (2) Topology improvement: The sneak circuit path can be cut off by changing the converter topology based on the characteristics of sneak circuit path. Although this method can eliminate the hazards of sneak circuits, changing the converter topology may create new sneak circuit paths or affect the converter performance. (3) Modulation optimization: The triggering of sneak circuit phenomenon is also related to the control method. Literature [23] devised an optimized duty cycle to suppress the sneak circuit phenomenon. This method can suppress the sneak circuit without changing circuit structure. (4) Switching device selection optimization: Literature [27] reduced the switching loss of SiC MOSFET with the help of existing parasitic components. The influence of parasitic parameters on switched-capacitor converters performance has been investigated in [28], and corresponding design methods have been proposed.
The selection of suitable sneak circuit elimination method should consider the converter actual situation. For converters with sneak circuits that have clear trigger conditions, parametric design, modulation optimization, and optimal selection of switching devices method can be selected. While, for converters with unclear sneak circuit trigger conditions, the topology improvement method would be a better choice.
However, the detailed study of trigger mechanism and suppression method of sneak circuit phenomenon in CLLC resonant converter requires accurate modeling, so the FHA analysis method is not applicable. To address the above problems, this paper adopts a graph-theory based method for analyzing, triggering and suppressing the CLLC sneak circuit phenomenon when considering parasitic parameters. The CLLC resonant converter is accurately modeled and analyzed in the time domain, and the method to suppress the appearance of sneak circuits is proposed. The contributions of this article are given as follows.
2) Through the time-domain modeling of CLLC converter, the sneak circuit phenomenon is analyzed in detail, and the negative effects of sneak circuit on system operation features and the sneak phenomenon are explained.
3) The trigger mechanism of the sneak modality of CLLC converter is investigated and listed in the form of a time series, which reveals the influence of the converter parameters as well as the modulation parameters on the converter operating state, and the suppression conditions are deduced to improve the efficiency as well as the reliability of CLLC converter.
In contrast to previous studies, the sneak modality of CLLC resonant converter is comprehensively modeled, analyzed, and suppressed in this paper to improve the system efficiency and reliability.
II The Sneak Circuit Paths Graph Analysis of CLLC Based on Current Direction and Switch State
Less
A. Graph-Theoretic Modeling of CLLC Converter With Parasitic Parameters
The CLLC resonant converter topology considering parasitic parameters is shown in Fig. 1(a). ${V}_{\text{in }}$ and ${V}_{\mathrm{o}}$ are the input and output voltages, respectively. Co is the output filter capacitor. Ro is load resistance. The turns ratio of transformer is $n : 1.{L}_{\mathrm{r}1}$ and ${L}_{\mathrm{r}2}$ are the primary and secondary side resonant inductors. ${C}_{\mathrm{r}1}$ and ${C}_{\mathrm{r}2}$ are the primary and secondary side resonant capacitors. ${L}_{\mathrm{m}}$ is the transformer excitation inductance. There are eight MOSFETs S1-S1 in CLLC converter, as well as antiparallel diodes D1-D8. Considering the parasitic capacitance of semiconductors, they are equivalent to the parasitic capacitance ${C}_{\text{oss }}$ in parallel with the MOSFETs. ${C}_{1} - {C}_{8}$ are connected in parallel with switches ${\mathrm{S}}_{1} - {\mathrm{S}}_{8}$.
The topology of CLLC is modeled as the directed graph in Fig. 1(b). The current and voltage directions labeled in Fig. 1(a) are defined as positive directions. The direction from node ${n}_{1}$ to node ${n}_{2}$ is the charging direction of capacitor ${C}_{1}$. The capacitor charging direction is defined as the positive direction, denoted as ${C}_{1 + }$. The edge from ${n}_{2}$ to ${n}_{1}$ is defined as the discharge direction and is denoted as ${C}_{1}$. Similarly, the charging and discharging directions of ${C}_{2} - {C}_{8}$ are defined in the same way. According to the graph theory, the connection matrices are established for both the primary and secondary sides of CLLC converter, as shown in (1) and (2).
$\left[\begin{array}{cccccc}1 & \mathrm{~S}_{1}+C_{1+} & \mathrm{S}_{3}+C_{3+} & V_{\mathrm{in}} & 0 & 0 \\\mathrm{D}_{1}+C_{1-} & 1 & 0 & \mathrm{~S}_{2}+C_{2+} & L_{\mathrm{r} 1+} & 0 \\\mathrm{D}_{3}+C_{3-} & 0 & 1 & \mathrm{~S}_{4}+C_{4+} & 0 & C_{\mathrm{r} 1-} \\V_{\mathrm{in}} & \mathrm{D}_{2}+C_{2-} & \mathrm{D}_{4}+C_{4-} & 1 & 0 & 0 \\0 & L_{\mathrm{r} 1-} & 0 & 0 & 1 & L_{\mathrm{m}+} \\0 & 0 & C_{\mathrm{r} 1+} & 0 & L_{\mathrm{m}-} & 1\end{array}\right]$
$\left[\begin{array}{cccc}1 & C_{5+} & C_{7+} & V_{\circ} \\\mathrm{D}_{5}+C_{5-} & 1 & L_{\mathrm{r} 2-}+C_{\mathrm{r} 2-} & C_{6+} \\\mathrm{D}_{7}+C_{7-} & L_{\mathrm{r} 2+}+C_{\mathrm{r} 2+} & 1 & C_{8+} \\V_{\circ} & \mathrm{D}_{6}+C_{6-} & \mathrm{D}_{8}+C_{8-} & 1\end{array}\right]$
When modeling the directed graph of CLLC, it is worth noting that the bidirectional CLLC converter operates in forward direction with ${\mathrm{S}}_{1}$ and ${\mathrm{S}}_{4}$ conduct synchronously on the primary side, ${\mathrm{S}}_{2}$ and ${\mathrm{S}}_{3}$ conduct complementary to ${\mathrm{S}}_{1}$ and ${\mathrm{S}}_{4}$, and the secondary side achieves current rectification by using the parasitic diode of MOSFETs. At the same time, to simplify the calculation of current path, ${L}_{\mathrm{m}}$ and the primary side winding of transformer are combined into ${L}_{\mathrm{m}}$ in the directed graph and connection matrix. The primary side current of the transformer is determined by its secondary side current.
Therefore, all circuit paths in CLLC converter can be found by the determinants of connection matrices (1) and (2). And feasible current paths can be selected based on the basic rules and modulation method of the circuit.
B. Current Analysis Based on Current Direction and Switch State
In practice, the current path between primary and secondary sides of CLLC converter is determined by ${i}_{\mathrm{p}}$ and ${i}_{\mathrm{s}}$. In normal operation, each mode of CLLC is mainly decided by the switching state (ON or OFF) and current direction.
According to the proposed method, all possible combinations of switching states and the corresponding normal circuits are listed in Table I. Sneak current circuits on primary and secondary sides are classified according to the direction of the current as shown in Table II. According to (1) and (2), the parasitic parameters can cause CLLC converter to generate different sneak circuits during actual operation. This may lead to unexpected operating modes during current conversion [22]. By connecting the primary and secondary side current paths, the complete sneak circuit paths of CLLC converter can be obtained. The complete sneak circuit operating mode during power conversion consists of charging and discharging parasitic capacitors on the same bridge arm. Since the CLLC converter adopts a symmetrical operation mode, only the positive half-cycle sneak operation mode is analyzed. The other half-cycle of the sneak circuit is symmetrical. The corresponding sneak circuit modes are shown in Table III. A complete model of the sneak circuit is developed by using the path analysis method based on current direction to characterize the dynamics of parasitic capacitors in CLLC converter, where the dynamic voltage of the parasitic capacitors excites the sneak circuit and degrades the performance of converter.
III. Sneak Modality Analysis
Less
In order to avoid the appearance of unexpected sneak modality, their trigger conditions need to be determined. Therefore, an unabridged time-domain model of CLLC is required. The converter modulation method affects the trigger conditions of sneak circuits, and since the quasi-resonant state can be regarded as a special state of the under-resonant state, it will be analyzed in two categories: under-resonant modulation and over-resonant modulation.
Before theoretical analysis, the following assumptions are made:
  1. 1) The parasitic capacitances ${C}_{1} - {C}_{8}$ of MOSFETs are equal and their values are ${C}_{\mathrm{{oss}}}$ ;

  1. 2) The value of the parasitic capacitance ${C}_{\text{oss }}$ is much smaller than the value of resonant capacitance ${C}_{\mathrm{r}}$ ;

  2. If the transformer ratio is $n : 1$ then ${n}^{2}{C}_{\mathrm{r}1} = {C}_{\mathrm{r}2},{L}_{\mathrm{r}1} = {n}^{2}{L}_{\mathrm{r}2}$. In designing, ${L}_{\mathrm{r}1} = {n}^{2}{L}_{\mathrm{r}2} = {L}_{\mathrm{r}},{C}_{\mathrm{r}1} = {C}_{\mathrm{r}2}/{n}^{2} = {C}_{\mathrm{r}}$.

A. Under-Resonant Modulation Time-Domain Modeling
The under-resonant operation waveforms of CLLC are shown in Fig. 2. Based on Table III, the possible current paths in under-resonant operation state are normal modality 1 to normal modality 2 and sneak modality 1 to sneak modality 7. To ensure the completeness of CLLC converter time-domain model, the time-domain modeling is required for normal modalities 1 and 2. Sneak modalities 4 and 5 end instantaneously, so they can be ignored when performing the time-domain analysis. Sneak modality 2 is triggered by sneak modalities 1 and 3, thus the time-domain modeling of sneak modalities 1 and 3 are required. Sneak modality 7 is triggered by sneak modality 6, so a time domain model of sneak modality 6 is needed. Therefore, the time-domain analysis is divided into three parts for discussion, as described in the following.
1) Normal Modality 1 and Normal Modality 2
The circuit diagrams of normal modalities 1 and 2, and their equivalent circuits are shown in Fig. 3. Based on the equivalent circuit, the voltage and current relationship expressions can be derived in (3).
$ \left\{ \begin{array}{l} {V}_{\text{in }} = {L}_{\mathrm{r}}\frac{\mathrm{d}{i}_{\mathrm{p}}\left(t\right) }{\mathrm{d}t} + {u}_{C1}\left(t\right) + {L}_{\mathrm{m}}\frac{\mathrm{d}{i}_{\mathrm{m}}\left(t\right) }{\mathrm{d}t},{L}_{\mathrm{m}}\frac{\mathrm{d}{i}_{\mathrm{m}}\left(t\right) }{\mathrm{d}t} = {L}_{\mathrm{r}}\frac{\mathrm{d}{i}_{\mathrm{s}}\left(t\right) }{\mathrm{d}t} + {u}_{C2}\left(t\right) + V \\ {i}_{\mathrm{p}}\left(t\right) = {i}_{\mathrm{s}}\left(t\right) + {i}_{\mathrm{m}}\left(t\right),{i}_{\mathrm{p}}\left(t\right) = {C}_{\mathrm{r}}\frac{\mathrm{d}{u}_{C1}\left(t\right) }{\mathrm{d}t},{i}_{\mathrm{s}}\left(t\right) = {C}_{\mathrm{r}}\frac{\mathrm{d}{u}_{C2}\left(t\right) }{\mathrm{d}t} \end{array}\right. $
Solving (3) by using the differential operator method yields (4)-(7).
$ {u}_{C1}\left(t\right) = {A}_{1}\cos \left({{\omega }_{A1}t}\right) + {A}_{2}\sin \left({{\omega }_{A1}t}\right) + {A}_{3}\cos \left({{\omega }_{A2}t}\right) + \\ {A}_{4}\sin \left({{\omega }_{A2}t}\right) + {V}_{\text{in }} \\ {u}_{C2}\left(t\right) = {A}_{1}\cos \left({{\omega }_{A1}t}\right) + {A}_{2}\sin \left({{\omega }_{A1}t}\right) - {A}_{3}\cos \left({{\omega }_{A2}t}\right) - \\ {A}_{4}\sin \left({{\omega }_{A2}t}\right) - {V}_{o} \\ {i}_{\mathrm{p}}\left(t\right) = - {C}_{\mathrm{r}}{\omega }_{A1}{A}_{1}\sin \left({{\omega }_{A1}t}\right) + {C}_{\mathrm{r}}{\omega }_{A1}{A}_{2}\cos \left({{\omega }_{A1}t}\right) - \\ {C}_{\mathrm{r}}{\omega }_{A2}{A}_{3}\sin \left({{\omega }_{A2}t}\right) + {C}_{\mathrm{r}}{\omega }_{A2}{A}_{4}\cos \left({{\omega }_{A2}t}\right) \\ {i}_{\mathrm{s}}\left(t\right) = - {C}_{\mathrm{r}}{\omega }_{A1}{A}_{1}\sin \left({{\omega }_{A1}t}\right) + {C}_{\mathrm{r}}{\omega }_{A1}{A}_{2}\cos \left({{\omega }_{A1}t}\right) + \\ {C}_{\mathrm{r}}{\omega }_{A2}{A}_{3}\sin \left({{\omega }_{A2}t}\right) - {C}_{\mathrm{r}}{\omega }_{A2}{A}_{4}\cos \left({{\omega }_{A2}t}\right) $
where ${\omega }_{A1},{\omega }_{A2}$ and ${A}_{1} - {A}_{4}$ are listed in Table IV. ${A}_{1} - {A}_{4}$ can be derived from (8).
$ {u}_{C1}\left({t}_{0}\right) = {u}_{C1}\left({t}_{0}\right),\frac{\mathrm{d}{u}_{C1}\left({t}_{0}\right) }{\mathrm{d}t} = \frac{{i}_{\mathrm{p}}\left({t}_{0}\right) }{{C}_{\mathrm{r}}},{u}_{C2}\left({t}_{0}\right) = {u}_{C2}\left({t}_{0}\right),\frac{\mathrm{d}{u}_{C2}\left({t}_{0}\right) }{\mathrm{d}t} = \frac{{i}_{\mathrm{s}}\left({t}_{0}\right) }{{C}_{\mathrm{r}}} $
where ${i}_{\mathrm{s}}\left({t}_{0}\right) = {i}_{\mathrm{p}}\left({t}_{0}\right) - {i}_{\mathrm{m}}\left({t}_{0}\right)$, due to current ${i}_{\mathrm{p}}\left({t}_{0}\right)$ is approximately equal to the current ${i}_{\mathrm{m}}\left({t}_{0}\right)$, which means ${i}_{\mathrm{s}}\left({t}_{0}\right) = 0$.
2) Sneak Modality 1 and Sneak Modality 3
Although the current direction on secondary side of sneak modalities 1 and modality 3 is different, they both have the same current path diagram and equivalent circuits, as shown in Fig. 4.
According to the equivalent circuit in Fig. 4 (b), the state equations can be derived in (9). The total capacitance value of ${C}_{\mathrm{r}}$ in series with ${C}_{\mathrm{{oss}}}$ is ${C}_{\mathrm{{oss}}}$, due to ${C}_{\mathrm{{oss}}} < < {C}_{\mathrm{r}}$. Therefore, ${u}_{\mathrm{{Coss}}}\left(t\right)$ $+ {u}_{C2}\left(t\right) = {u}_{2}\left(t\right)$.
$ \left\{ \begin{array}{l} {V}_{\text{in }} = {L}_{\mathrm{r}}\frac{\mathrm{d}{i}_{\mathrm{p}}\left(t\right) }{\mathrm{d}t} + {u}_{C1}\left(t\right) + {L}_{\mathrm{m}}\frac{\mathrm{d}{i}_{\mathrm{m}}\left(t\right) }{\mathrm{d}t},{L}_{\mathrm{m}}\frac{\mathrm{d}{i}_{\mathrm{m}}\left(t\right) }{\mathrm{d}t} = {L}_{\mathrm{r}}\frac{\mathrm{d}{i}_{\mathrm{s}}\left(t\right) }{\mathrm{d}t} + {u}_{2}\left(t\right) \\ {i}_{\mathrm{p}}\left(t\right) = {i}_{\mathrm{s}}\left(t\right) + {i}_{\mathrm{m}}\left(t\right),{i}_{\mathrm{p}}\left(t\right) = {C}_{\mathrm{r}}\frac{\mathrm{d}{u}_{C1}\left(t\right) }{\mathrm{d}t},{i}_{\mathrm{s}}\left(t\right) = {C}_{\mathrm{{oss}}}\frac{\mathrm{d}{u}_{2}\left(t\right) }{\mathrm{d}t} \end{array}\right. $
Solving (9) by using the differential operator method yields $\left({10}\right) - \left({13}\right)$.
$\begin{aligned}u_{C 1}(t)= & B_{1} \cos \left(\omega_{B 1} t\right)+B_{2} \sin \left(\omega_{B 1} t\right)+ \\& B_{3} \cos \left(\omega_{B 2} t\right)+B_{4} \sin \left(\omega_{B 2} t\right)+V_{\mathrm{in}}\end{aligned}$
$\begin{aligned}u_{2}(t)= & \frac{\left(L_{\mathrm{r}}+L_{\mathrm{m}}\right)}{L_{\mathrm{m}}} \frac{C_{\mathrm{r}}}{C_{\text {oss }}}\left[B_{1} \cos \left(\omega_{B 1} t\right)+B_{2} \sin \left(\omega_{B 1} t\right)\right]- \\& \frac{L_{\mathrm{r}}+L_{\mathrm{m}}}{L_{\mathrm{m}}}\left[B_{3} \cos \left(\omega_{B 2} t\right)+B_{4} \sin \left(\omega_{B 2} t\right)\right]\end{aligned}$
$\begin{aligned}i_{\mathrm{s}}(t)= & \frac{L_{\mathrm{r}}+L_{\mathrm{m}}}{L_{\mathrm{m}}} C_{\mathrm{r}} \omega_{B 1}\left[-B_{1} \sin \left(\omega_{B 1} t\right)+B_{2} \cos \left(\omega_{B 1} t\right)\right]- \\& \frac{L_{\mathrm{r}}+L_{\mathrm{m}}}{L_{\mathrm{m}}} C_{\mathrm{oss}} \omega_{B 2}\left[-B_{3} \sin \left(\omega_{B 2} t\right)+B_{4} \cos \left(\omega_{B 2} t\right)\right]\end{aligned}$
$\begin{aligned}i_{\mathrm{p}}(t)= & C_{\mathrm{r}} \omega_{B 1}\left[-B_{1} \sin \left(\omega_{B 1} t\right)+B_{2} \cos \left(\omega_{B 1} t\right)\right]+ \\& C_{\mathrm{r}} \omega_{B 2}\left[-B_{3} \sin \left(\omega_{B 2} t\right)+B_{4} \cos \left(\omega_{B 2} t\right)\right]\end{aligned}$
where ${\omega }_{B1},{\omega }_{B2}$ and ${B}_{1} - {B}_{4}$ are listed in Table IV. ${B}_{1} - {B}_{4}$ can be calculated by (14).
$ {u}_{C1}\left({t}_{1}\right) = {u}_{C1}\left({t}_{1}\right),\frac{\mathrm{d}{u}_{C1}\left({t}_{1}\right) }{\mathrm{d}t} = \frac{{i}_{\mathrm{p}}\left({t}_{1}\right) }{{C}_{\mathrm{r}}},{u}_{2}\left({t}_{1}\right) = {u}_{C2}\left({t}_{1}\right) + {V}_{\mathrm{o}},\frac{\mathrm{d}{u}_{2}\left({t}_{1}\right) }{\mathrm{d}t} = \frac{{i}_{\mathrm{s}}\left({t}_{1}\right) }{{C}_{\text{oss }}} $
where ${i}_{\mathrm{s}}\left({t}_{1}\right) = {i}_{\mathrm{p}}\left({t}_{1}\right) - {i}_{\mathrm{m}}\left({t}_{1}\right)$, due to current ${i}_{\mathrm{p}}\left({t}_{1}\right)$ is approximately equal to the current ${i}_{\mathrm{m}}\left({t}_{1}\right)$, which means ${i}_{\mathrm{s}}\left({t}_{1}\right) = 0$. Sneak modality 2 is a situation that should be avoided, so there is no need to model it in the time domain.
3) Sneak Modality 6
The current path circuit diagram and equivalent circuit of Sneak modality 6 are shown in Fig. 5. Based on Fig. 5 (b), the voltage and current relationship expressions can be derived in the followings.
$ \left\{ \begin{array}{l} - {V}_{\mathrm{m}} = {L}_{\mathrm{r}}\frac{\mathrm{d}{i}_{\mathrm{p}}\left(t\right) }{\mathrm{d}t} + {u}_{{c}_{1}}\left(t\right) + {L}_{\mathrm{m}}\frac{\mathrm{d}{i}_{\mathrm{m}}\left(t\right) }{\mathrm{d}t},{L}_{\mathrm{m}}\frac{\mathrm{d}{i}_{\mathrm{m}}\left(t\right) }{\mathrm{d}t} = {L}_{\mathrm{r}}\frac{\mathrm{d}{i}_{\mathrm{r}}\left(t\right) }{\mathrm{d}t} + {u}_{{c}_{2}}\left(t\right) - {V}_{\mathrm{o}} \\ {i}_{\mathrm{p}}\left(t\right) = {i}_{\mathrm{s}}\left(t\right) + {i}_{\mathrm{m}}\left(t\right),{i}_{\mathrm{p}}\left(t\right) = {C}_{\mathrm{r}}\frac{\mathrm{d}{u}_{{c}_{1}}\left(t\right) }{\mathrm{d}t},{i}_{\mathrm{s}}\left(t\right) = {C}_{\mathrm{r}}\frac{\mathrm{d}{u}_{{c}_{2}}\left(t\right) }{\mathrm{d}t} \end{array}\right. $
$\begin{aligned}u_{C 1}(t)= & J_{1} \cos \left(\omega_{J 1} t\right)+J_{2} \sin \left(\omega_{J 1} t\right)+ \\& J_{3} \cos \left(\omega_{J 2} t\right)+J_{4} \sin \left(\omega_{J 2} t\right)-V_{\mathrm{in}}\end{aligned}$
$\begin{aligned}u_{C 2}(t)= & J_{1} \cos \left(\omega_{J 1} t\right)+J_{2} \sin \left(\omega_{J 1} t\right)- \\& J_{3} \cos \left(\omega_{J 2} t\right)-J_{4} \sin \left(\omega_{J 2} t\right)+V_{0}\end{aligned}$
$\begin{aligned}i_{\mathrm{p}}(t)= & -J_{1} \omega_{J 1} C_{\mathrm{r}} \sin \left(\omega_{J 1} t\right)+J_{2} \omega_{J 1} C_{\mathrm{r}} \cos \left(\omega_{J 1} t\right)- \\& J_{3} \omega_{J 2} C_{\mathrm{r}} \sin \left(\omega_{J 2} t\right)+J_{4} \omega_{J 2} C_{\mathrm{r}} \cos \left(\omega_{J 2} t\right)\end{aligned}$
where ${\omega }_{J1},{\omega }_{J2}$ and ${J}_{1} - {J}_{4}$ are listed in Table IV. ${J}_{1} - {J}_{4}$ can be derived by solving (19).
$ {u}_{c1}\left({t}_{2}\right) = {u}_{c1}\left({t}_{2}\right),\frac{\mathrm{d}{u}_{c1}\left({t}_{2}\right) }{\mathrm{d}t} = \frac{{i}_{\mathrm{p}}\left({t}_{2}\right) }{{C}_{\mathrm{r}}},{u}_{c2}\left({t}_{2}\right) = {u}_{c2}\left({t}_{2}\right),\frac{\mathrm{d}{u}_{c2}\left({t}_{2}\right) }{\mathrm{d}t} = \frac{{i}_{\mathrm{s}}\left({t}_{2}\right) }{{C}_{\mathrm{r}}} $
Due to the current ${i}_{\mathrm{p}}\left({t}_{2}\right)$ is approximately equal to the current ${i}_{\mathrm{m}}\left({t}_{2}\right)$, which indicates ${i}_{\mathrm{s}}\left({t}_{2}\right) = {i}_{\mathrm{p}}\left({t}_{2}\right) - {i}_{\mathrm{m}}\left({t}_{2}\right) = 0$.
B. Over-Resonant Modulation Time-Domain Modeling
According to Table III, the possible current paths in over-resonant operating state are normal modality 1 to normal modality 2 and sneak modality 5 to sneak modality 9. The circuits of normal modalities 1 and 2 in over-resonant state are the same as the circuits in under-resonant state. Sneak modalities 5 and 8 end instantaneously, and they can be ignored when performing the time-domain analysis. Sneak modality 7 is triggered jointly by sneak modalities 6 and 9, and thus sneak modalities 6 and 9 need to be modeled in the time domain. The equivalent circuit of sneak modality 6 at over-resonance is the same as that of the under-resonant state, except that the initial value of time entry is different for the calculation and solution. The time-domain analysis of sneak modality 9 at over-resonance is described in the following. The voltage and current waveforms during the over-resonant operating condition are shown in Fig. 6. The current path diagram and equivalent circuit of sneak modality 9 are shown in Fig. 7.
Based on Fig. 7(b), the voltage and current relationship expressions are obtained in the following.
$ \left\{ \begin{array}{l} - {V}_{\mathrm{n}} = {L}_{\mathrm{r}}\frac{\mathrm{d}{i}_{\mathrm{p}}\left(t\right) }{\mathrm{d}t} + {u}_{{c}_{1}}\left(t\right) + {L}_{\mathrm{m}}\frac{\mathrm{d}{i}_{\mathrm{m}}\left(t\right) }{\mathrm{d}t},{L}_{\mathrm{m}}\frac{\mathrm{d}{i}_{\mathrm{m}}\left(t\right) }{\mathrm{d}t} = {L}_{\mathrm{r}}\frac{\mathrm{d}{i}_{\mathrm{r}}\left(t\right) }{\mathrm{d}t} + {u}_{{c}_{2}}\left(t\right) + {V}_{ \circ } \\ {i}_{\mathrm{p}}\left(t\right) = {i}_{\mathrm{s}}\left(t\right) + {i}_{\mathrm{m}}\left(t\right),{i}_{\mathrm{p}}\left(t\right) = {C}_{\mathrm{r}}\frac{\mathrm{d}{u}_{{c}_{1}}\left(t\right) }{\mathrm{d}t},{i}_{\mathrm{s}}\left(t\right) = {C}_{\mathrm{r}}\frac{\mathrm{d}{u}_{{c}_{2}}\left(t\right) }{\mathrm{d}t} \end{array}\right. $
$ {u}_{C1}\left(t\right) = {K}_{1}\cos \left({{\omega }_{K1}t}\right) + {K}_{2}\sin \left({{\omega }_{K1}t}\right) + \\ {K}_{3}\cos \left({{\omega }_{K2}t}\right) + {K}_{4}\sin \left({{\omega }_{K2}t}\right) - {V}_{\text{in }} \\ {u}_{C2}\left(t\right) = {K}_{1}\cos \left({{\omega }_{K1}t}\right) + {K}_{2}\sin \left({{\omega }_{K1}t}\right) + \\ {K}_{3}\cos \left({{\omega }_{K2}t}\right) - {K}_{4}\sin \left({{\omega }_{K2}t}\right) - {V}_{\mathrm{o}} \\ {i}_{\mathrm{p}}\left(t\right) = - {K}_{1}{\omega }_{K1}{C}_{\mathrm{r}}\sin \left({{\omega }_{K1}t}\right) + {K}_{2}{\omega }_{K1}{C}_{\mathrm{r}}\cos \left({{\omega }_{K1}t}\right) - \\ {K}_{3}{\omega }_{K2}{C}_{\mathrm{r}}\sin \left({{\omega }_{K2}t}\right) + {K}_{4}{\omega }_{K2}{C}_{\mathrm{r}}\cos \left({{\omega }_{K2}t}\right) $
where ${\omega }_{K1},{\omega }_{K2}$ and substituting the initial values yields ${K}_{1} - {K}_{4}$, are au listed in Table IV.
IV. Sneak Circuit Phenomenon and Trigger Mechanisms and Suppression
Less
According to the combination and trigger form of these sneak operation modes, there are four sneak circuit phenomena in CLLC resonant converter, which are listed in Table V.
A. Sneak Circuit Phenomenon 1
During under-resonant operation, the normal modality between ${t}_{1} - {t}_{2}$ is the alternating operation of sneak modalities 1 and 3. And the appearance of sneak modality 2 will be triggered when the parasitic capacitance voltage ${u}_{\mathrm{S}7}$ of switch ${\mathrm{S}}_{7}$ is equal to zero. At this time, the current flows through parasitic diode during the non-power transfer duration, generates a non-essential power loss. Thus, the appearance of sneak modality 2 reduces the efficiency of CLLC converter. The key operation waveforms when sneak modality 2 is triggered are shown in Fig. 8(a).
Based on the time-domain model established in Section III-A and (12), since ${\omega }_{\mathrm{B}1} > > {\omega }_{\mathrm{B}2},{i}_{\mathrm{s}}\left(t\right)$ can be derived as (24), ${u}_{\mathrm{S}7}$ can be solved as shown in (25).
$ {i}_{\mathrm{s}}\left(t\right) = \frac{{L}_{\mathrm{r}} + {L}_{\mathrm{m}}}{{L}_{\mathrm{m}}}{C}_{\mathrm{r}}{\omega }_{B1}\left\lbrack {-{B}_{1}\sin \left({{\omega }_{B1}t}\right) + {B}_{2}\cos \left({{\omega }_{B1}t}\right) }\right\rbrack $
$\begin{aligned}u_{\mathrm{S} 7}(t)= & \frac{1}{C_{\mathrm{oss}}} \int \frac{i_{\mathrm{s}}}{2} \mathrm{~d} t=\frac{1}{2} \frac{L_{\mathrm{r}}+L_{\mathrm{m}}}{L_{\mathrm{m}}} \frac{C_{\mathrm{r}}}{C_{\mathrm{oss}}}\left[B_{1} \cos \left(\omega_{B 1} t\right)+\right. \\& \left.B_{2} \sin \left(\omega_{B 1} t\right)\right]+E\end{aligned}$
$2 u_{\mathrm{S} 7}=\left[u_{C 1}\left(t_{1}\right)+u_{C 2}\left(t_{1}\right)-V_{\mathrm{in}}+V_{\mathrm{o}}\right] \cos \left(\omega_{B 1} t\right)+2 E$
$2 E=V_{o}-u_{C 2}\left(t_{1}\right)+V_{\mathrm{in}}-u_{C 1}\left(t_{1}\right)$
$u_{\mathrm{S} 7 \text { min }}=E-U_{\mathrm{S} 7}$
$C_{\mathrm{r}}>\frac{P_{\mathrm{o}}}{2 V_{\mathrm{o}}^{2} f_{\mathrm{r}}}$
Resonant capacitance needs to satisfy (29) when designing the CLLC converter in order to avoid the sneak circuit phenomenon 1. The influence of ${C}_{\mathrm{{oss}}}$ on ${u}_{\mathrm{S}7}$ is ignored in the derivation, but the value of ${C}_{\text{oss }}$ is proportional to the oscillation amplitude of ${u}_{\mathrm{S}7}$. Thus, the selection of switches with smaller parasitic capacitance helps to avoid the sneak modality 2.
B. Sneak Circuit Phenomenon 2
Due to sneak modality 7 is triggered, sneak circuit phenomenon 2 occurs during ${t}_{2} - {t}_{3}$ period in the under-resonant state. When ${i}_{\mathrm{p}} = 0$, the primary side switch is fully closed, then sneak modality 7 is triggered, at this time the ZVS of primary side switch is disabled. The key waveforms in sneak circuit phenomenon 2 is shown in Fig. 8(b).
To achieve reliable ZVS on the primary side of CLLC converter, it is necessary to ensure that the switches change phase before ${i}_{\mathrm{p}}$ crosses zero. Therefore, the timing of ${i}_{\mathrm{p}}$ crosses zero needs to be analyzed. The maximum and minimum value of ${t}_{\text{dead }}$ can be found according to (18) and (30). ${u}_{C1}\left({t}_{2}\right) = {u}_{C1}\left({t}_{1}\right)$ $+ {I}_{\mathrm{m}}\left({{T}_{\mathrm{s}} - {T}_{\mathrm{r}}}\right) /\left({2{C}_{\mathrm{r}}}\right),{u}_{C2}\left({t}_{2}\right) = {u}_{C2}\left({t}_{1}\right)$, where ${T}_{\mathrm{s}}$ is the switch period and ${T}_{\mathrm{r}}$ is the resonant period.
$ {i}_{\mathrm{p}}\left({t}_{2}\right) = {I}_{\mathrm{m}},{i}_{\mathrm{p}}\left({t}_{3}\right) = 0,{t}_{\text{dead }\_ \max } = {t}_{3} - {t}_{2},{t}_{\text{dead }\_ \min } = 8{C}_{\mathrm{{oss}}}{L}_{\mathrm{m}}{f}_{\mathrm{r}} $
where ${I}_{\mathrm{m}}$ is the peak value of the excitation inductor current, ${f}_{\mathrm{r}}$ is the resonant frequency.
$ {I}_{\mathrm{m}} = \frac{{V}_{\mathrm{o}}}{4{L}_{\mathrm{m}}{f}_{\mathrm{r}}} $
C. Sneak Circuit Phenomenon 3
Due to sneak modality 2 is triggered simultaneously with sneak modality 7, then sneak circuit phenomenon 3 occurs. And it is the worst operation case of CLLC converter, resulting in large power loss. The trigger conditions of sneak modalities 2 and 7 have been analyzed in Section III and will not be repeated here. The key operation waveforms during this phenomenon are shown in Fig. 8(c).
D. Sneak Circuit Phenomenon 4
When CLLC converter operates in the over-resonant state, sneak circuit phenomenon 4 is triggered by sneak modality 7, where modality 7 is co-triggered by both sneak modalities 6 and 9 jointly. Currently, the ZVS of primary-side switches in CLLC converter fails. To avoid the appearance of sneak circuit phenomenon 4, the dead time must be less than the operating time of sneak modalities 9 and 6. The key waveforms at this stage are presented in Fig. 8(d). Define the operation time of sneak modalities 9 and 6 as $\Delta {t}_{1}$ and $\Delta {t}_{2}$, respectively. Then, $\Delta {t}_{1}$ can be calculated according to (23).
$ {i}_{\mathrm{p}}\left({t}_{1}\right) = {i}_{\mathrm{p}}\left({t}_{1}\right),\;{i}_{\mathrm{p}}\left({t}_{2}\right) = {I}_{\mathrm{m}},\;\Delta {t}_{1} = {t}_{2} - {t}_{1} $
where ${I}_{\mathrm{m}} = {V}_{\mathrm{{in}}}/\left({4{L}_{\mathrm{m}}{f}_{\mathrm{s}}}\right),{f}_{\mathrm{s}}$ is the switching frequency.
Based on (18), $\Delta {t}_{2}$ can be calculated as
$ {i}_{\mathrm{p}}\left({t}_{2}\right) = {I}_{\mathrm{m}},\;{i}_{\mathrm{p}}\left({t}_{3}\right) = 0,\Delta {t}_{2} = {t}_{3} - {t}_{2} $
From (32) and (33), the maximum value of dead time can be calculated by
$ {t}_{\text{dead }\_ \max } = \Delta {t}_{1} + \Delta {t}_{2} $
In order to ensure reliable ZVS on the primary side switches, the minimum value of ${t}_{\text{dead }}$ is
$ {t}_{\text{dead }\_ \min } = 8{C}_{\mathrm{{oss}}}{L}_{\mathrm{m}}{f}_{\mathrm{s}} $
V. Experimental Verification
Less
In this section, a CLLC resonant converter prototype with the rated power of $1\mathrm{\;{kW}}$ is built for experimental verification. The detailed power circuit specifications are listed in Table VI, and the hardware platform is outlined in Fig. 9.
In order to verify the trigger conditions for the occurrence of sneak circuits, four types of sneak circuit phenomena are triggered under different conditions in the experiment, and the measured experimental waveforms are shown in Fig. 10(a)-(d), the normal operation waveforms are shown in Fig. 10(e)-(f).
By using the parameters in Table VI with a dead time set to ${300}\mathrm{\;{ns}}$, and the load resistance is ${14.4\Omega }$ in the converter. As shown in Fig. 10(a), the sneak circuit phenomenon 1-modality 2 occurs. During the oscillation of current ${i}_{\mathrm{s}}$ around $0\mathrm{\;A}$, the parasitic capacitance of switches S5-S8 is continuously charged and discharged. When the voltage across C5-C8 is reduced to 0 V, the parasitic diodes D5-D8 become conductive, resulting in unnecessary losses.
The converter adopts the parameters in Table VII, and the load resistance is ${28.8\Omega }$. By using the theoretical calculations in Section IV, sneak modality 7 appears when ${t}_{\text{dead }} = {2.27\mu }\mathrm{s}$. And the deadtime is set to ${2.1\mu }\mathrm{s}$ in the experiment. As shown in Fig. 10(b), the CLLC converter operates in sneak circuit phenomena 2-modality 7. Due to the large dead time set for the primary side switches, the current ${i}_{\mathrm{p}}$ oscillates around $0\mathrm{\;A}$, continuously charging and discharging S1-S4. If the switches turn on when the drain-source voltage is not $0\mathrm{\;V}$, the switches transition from ZVS to hard switching, resulting in increased switching losses. Under sneak circuit phenomenon 2, although the current ${i}_{\mathrm{s}}$ oscillating around $0\mathrm{\;A}$, continuously charging and discharging S5-S8, the voltage across C5-C8 does not reach $0\mathrm{\;V}$. Consequently, the parasitic diodes D5-D8 do not conduct.
By adopting the parameters in Table VI, the deadtime is set to ${1.44\mu }\mathrm{s}$ and the load resistance is ${14.4\Omega }$. Sneak circuit phenomenon 2 appears when ${t}_{\text{dead }} = {0.8\mu }\mathrm{s}$. As shown in Fig. 10(c), CLLC converter operates in sneak circuit phenomena 3. It includes sneak modality 2 and modality 7. The primary-side switch ZVS fails and the secondary-side D5-D8 conduct in the non-power-transfer phase.
As shown in Fig. 10(d), By adopting the parameters in Table VI, CLLC converter operates in the over-resonance mode. By applying the theoretical calculations in Section IV and the load resistance is ${18\Omega }$, sneak modality 7 appears when ${t}_{\text{dead }} = {1.17\mu }\mathrm{s}$, and experimentally sneak modality 7 appears at ${t}_{\text{dead }} = {1.14\mu }\mathrm{s}$. When the sneak circuit phenomenon 4 occurs, the sneak modality 7 appears and the primary side switch ZVS fails.
The above four phenomena of sneak circuits will lead to lower efficiency of the CLLC converter, so the parameters of the converter are optimized and designed according to the method in Section IV. The parameters shown in Table VII are satisfied (29). Fig. 10(e) shows the normal operating waveforms for the under-resonant operating state. The converter adopts the parameters in Table VII, and the deadtime is set to 300 ns. The S5-S8 are continuously charged and discharged during the oscillation of current ${i}_{\mathrm{s}}$ around $0\mathrm{\;A}$. The voltage across C5-C8 does not drop to $0\mathrm{\;V}$ and D5-D8 are not conducted. Primary side switches S1-S4 operate in the ZVS state. Neither sneak phenomenon 1 nor sneak phenomenon 2 exists, i.e., sneak phenomenon 3 does not exist.
Fig. 10(f) shows the normal operating waveforms for the over-resonant operating state. The converter adopts the parameters in Table VI, and the deadtime is set to ${300}\mathrm{{ns}}$. Primary side switches S1-S4 operate in the ZVS state. Sneak phenomenon 4 does not exist.
Fig. 11 shows the efficiency curve of the CLLC converter with Table VI parameters. The converter adopts the parameters in Table VI, and it operates in the under-resonant state, the dead time of the converter is set to ${t}_{\text{deadl }} = {300}$ ns (blue line) and ${t}_{\mathrm{{dead}}2} > {1.4\mu }\mathrm{s}$ (yellow line), respectively. As shown in Fig. 11(a), the blue line is the efficiency curve when sneak circuit phenomenon 1 is present, and the yellow line is the efficiency curve when both sneak circuit phenomenons 1 and 2 are present, i.e., when sneak circuit phenomenon 3 is present. By setting the dead time appropriately, sneak circuit phenomenon 2 can be eliminated and efficiency can be improved.
As shown in Fig. 11(b), the converter adopts the parameters in Table VI, and it operates in the over-resonant state, ${t}_{\text{deadl }} =$ ${300}\mathrm{\;{ns}}$ (blue line) and ${t}_{\mathrm{{dead}}2} = {1.14\mu }\mathrm{s}$ (red line), respectively. When the dead time is set too large, it will trigger the sneak circuit phenomenon 4 resulting in the converter primary-side switches fail to realize ZVS, which also leads to the reduction of converter efficiency. By setting the dead time reasonably, the sneak circuit phenomenon 4 can be eliminated and the efficiency can be improved.
VI. Conclusion
Less
The graph theory-based sneak circuit particularity analysis, trigger mechanism and suppression method for CLLC resonant converter are studied in this paper. A current-based sneak circuit classification method is proposed, and an accurate sneak circuit analysis is realized by combining the relationship between the primary-side and secondary-side currents. In addition, the CLLC time-domain model considering parasitic parameters is investigated, nine sneak circuit modalities and four sneak circuit phenomena of CLLC converter are analyzed. The higher-order oscillations of voltage and current are also described in detail. During primary-side current and secondary-side current intermittency, there exists a current that charges and discharges inside the parasitic capacitor. The above sneak modality analysis helps to predict all possible sneak circuit phenomena.
Moreover, the trigger mechanism is introduced by time-domain analysis, and a general method to suppress the sneak circuit phenomenon is proposed to improve the reliability and efficiency of CLLC resonant converter operation by optimizing modulation parameters and the converter parameter design. The proposed suppression method avoids unnecessary power losses in the CLLC converter and effectively suppresses the oscillations of voltage and current waveforms.
Compared with previous research articles, the proposed method provides a more accurate model, a more detailed trigger mechanism and practical suppression method to improve the efficiency as well as the stability of CLLC converter. In addition, this method can be extended and applied to model and analyze other various resonant converters.
Funding
Less
  • State Key Laboratory of HVDC(SKLHVDC-2023-KF-11)
References
Less
[1]
A. Emadi , Y. J. Lee , K. Rajashekara . "Power electronics and motor drives in electric, hybrid electric, and plug-in hybrid electric vehicles", in IEEE Transactions on Industrial Electronics, vol. 55, no. 6, pp. 2237–2245, Jun. 2008.
[2]
W. Kramer , S. Chakraborty , B. Kroposki , A. Hoke , G. Martin , T. Markel . "Grid interconnection and performance testing procedures for vehicle-to-grid (V2G) power electronics. National Renewable Energy Laboratory, 2012. pp.1-8.
[3]
Z. U. Zahid , Z. M. Dalala , R. Chen , B. Chen , J. -S. Lai . "Design of bidirectional DC-DC resonant converter forvehicle-to-grid (V2G) applications", in IEEE Transactions on Transportation Electrification, vol. 1,no. 3, pp. 232–244, Oct. 2015.
[4]
M. Liu , X. Wang , J. Xu . "Design methodology of SiC MOSFET based bidirectional CLLC resonant converter for wide battery voltage range",in Proceedings of 2021 IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia (WiPDA Asia), Wuhan, China, 2021,pp. 423–427.
[5]
W. Chen , P. Rong , Z. Lu . "Snubberless bidirectional DC-DC converter with new CLLC resonant tank featuring minimized switching loss", in IEEE Transactions on Industrial Electronics, vol. 57, no. 9, pp.3075–3086, Sept. 2010.
[6]
K. -B. Park , B. -H. Lee , G. -W. Moon , M. -J. Youn . "Analysis on center-tap rectifier voltage oscillation of LLC resonant converter", in IEEE Transactions on Power Electronics, vol. 27, no. 6, pp. 2684–2689,Jun. 2012.
[7]
K. Sobe , T. Basler , B. Klobucar . "Characterization of the parasitic turn-on behavior of discrete CoolSiC MOSFETs,in Proceedings of PCIM Europe 2019; International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, Nuremberg, Germany, 2019, pp. 1–7.
[8]
J.-H. Jung , H. -S. Kim , M. -H. Ryu , J. -W. Baek . "Design methodology of bidirectional CLLC resonant converter for high-frequency isolation of DC distribution systems", in IEEE Transactions on Power Electronics, vol. 28, no. 4, pp. 1741–1755, Apr. 2013.
[9]
J. Wang , H. S. -H. Chung , R. T. -H. Li . "Characterization and exper-imental assessment of the effects of parasitic elements on the MOSFET switching performance", in IEEE Transactions on Power Electronics, vol. 28, no. 1, pp. 573–590, Jan. 2013.
[10]
D. N. Dalal , N. Christensen , A. B. Jørgensen , J. K. Jørgensen , S. Bęczkowski , S. Munk-Nielsen , C. Uhrenfeldt . "Impact of power module parasitic capacitances on medium-voltage SiC MOSFETS switching transients", in IEEE Journal of Emerging and Selected Topics in Power Electronics, vol. 8, no. 1, pp. 298–310, Mar. 2020.
[11]
S. Wei , Z. Zhao , L. Yuan , W. Wen , K. Chen . "Voltage oscillation suppression for the high-frequency bus in modular-multiactive-bridge converter", in IEEE Transactions on Power Electronics, vol. 36, no. 9,pp. 9737–9742, Sept. 2021.
[12]
A. Deshpande F. Luo . "Practical design considerations for a Si IGBT + SIC MOSFET hybrid switch: Parasitic interconnect influences, cost, and current ratio optimization", in IEEE Transactions on Power Electronics, vol. 34, no. 1, pp. 724-737, Jan. 2019.
[13]
T. O. Olowu , H. Jafari , I. Peirano , M. Mahmoudi , A. Sarwat . "Para-sitc parameter analysis of high frequency transformer for series resonant converter with experimental validation,in Proceedings of 2021 IEEE Transportation Electrification Conference & Expo (ITEC), Chicago, IL,USA, 2021, pp. 15–19.
[14]
Y. Cao , M. Ngo , D. Dong , R. Burgos . "The ZVS transition analysis and optimization for CLLC-type resonant DC transformer,in Proceedings of 2021 IEEE Energy Conversion Congress and Exposition (ECCE), Vancouver, BC, Canada, 2021, pp. 3126–3133.
[15]
D. Sha , Y. Zhao , D. Zhang . "ZVS-interleaved synchronous buck DC-DC converter with a coupled inductor by varying switching frequen-cy and deadtime", in IEEE Transactions on Power Electronics, vol. 37,no. 7, pp. 8190–8198, Jul. 2022.
[16]
X. Yang , C. Yan , P. Wen , Y. Liu , T. Q. Zheng , T. Takaku , S. Iga-rashi . "Improved phase shift control for SiC-MOSFET based resonant switched-capacitor converter with parasitics consideration", in IEEE Transactions on Industry Applications, vol. 56, no. 4, pp. 3995–4006,Jul.-Aug. 2020.
[17]
J. P. Rankin . "Sneak-circuit analysis", in Nucl. Safety, vol. 14, no. 5, pp.461–469, 1973.
[18]
B. Zhang D. Qiu . "Sneak circuits in power converters: Concept, principle and application", in CPSS Transactions on Power Electronics and Applications, vol. 2, no. 1, pp. 68–75, 2017.
[19]
B. Zhang , D. Qiu , G. Yi . "Multiple operating mode analysis of pow-er converter based on graph theory", in Chinese Journal of Electrical Engineering, vol. 1, no. 1, pp. 70–77, Dec. 2015.
[20]
B. Zhang D. Qiu . "Sneak circuit path analysis method for power electronic converters, in Sneak Circuits of Power Electronic Converters, Sinapare : John wiely & Sons Singapore Pte. Ltd., 2014, pp. 159–197.
[21]
Y. Li , J. Kuprat , Y. Li , M. Liserre . "Graph-theory-based derivation, modeling, and control of power converter systems", in IEEE Journal of Emerging and Selected Topics in Power Electronics, vol. 10, no. 6, pp.6557–6571, Dec. 2022.
[22]
M. Li , B. Zhang , D. Qiu , G. Zhang . "Sneak circuit phenomena in a DCM boost converter considering parasitic parameters", in IEEE Transactions on Power Electronics, vol. 32, no. 5, pp. 3946–3958, May 2017.
[23]
M. Li , B. Zhang , D. Qiu . "Sneak circuit analysis for a DCM flyback DC-DC converter considering parasitic parameters,in Proceedings of 2016 IEEE 8th International Power Electronics and Motion Control Conference (IPEMC-ECCE Asia), Hefei, 2016, pp. 1151–1155.
[24]
G. A. Mudiyanselage , N. Keshmiri , A. Emadi . "A review of DC-DC resonant converter topologies and control techniques for electric vehicle applications", in IEEE Open Journal of Power Electronics, vol. 4, pp.945–964, 2023.
[25]
J. Hong , X. Deng , G. Zhang , Z. Huang , X. Li , Y. Zhang . "Sneak circuit identification of an improved boost converter with soft-switching realization", in IEEE Journal of Emerging and Selected Topics in Power Electronics, vol. 7, no. 4, pp. 2394–2402, Dec. 2019.
[26]
M. Lu , X. Li , G. Chen . "A hybrid control of a semidual-active-bridge DC-DC converter with minimum current stress", in IEEE Transactions on Power Electronics, vol. 35, no. 3, pp. 3085–3096, Mar. 2020.
[27]
P. Nayak K. Hatua . "Parasitic inductance and capacitance-assisted active gate driving technique to minimize switching loss of SiC MOS-FET", in IEEE Transactions on Industrial Electronics, vol. 64, no. 10,pp. 8288–8298, Oct. 2017.
[28]
Y. Ye K. W. E. Cheng . "Analysis and optimization of switched capacitor power conversion circuits with parasitic resistances and induc-tances", in IEEE Transactions on Power Electronics, vol. 32, no. 3, pp.2018–2028, Mar. 2017.
Appendix
Less
Year 2025 volume 10 Issue 1
PDF
357
198
Cite this Article
BibTeX
Article Info
doi: 10.24295/CPSSTPEA.2025.00003
  • Receive Date：2024-09-06
  • Online Date：2025-07-05
  • Published：2025-03-10
Article Data
Affiliations
History
  • Received：2024-09-06
  • Revised：2024-12-09
  • Accepted：2025-01-03
Funding
State Key Laboratory of HVDC(SKLHVDC-2023-KF-11)
Affiliations
    1 Nanjing University of Aeronautics and Astronautics College of Automation Engineering Nanjing 210016 China
    2 Electric Power Research Institute of China Southern Power Grid State Key Laboratory of HVDC Guangzhou 510640 China

Corresponding:

Xiaoquan Zhu.
References
Share
https://castjournals.cast.org.cn/joweb/dldzjs/EN/10.24295/CPSSTPEA.2025.00003
Share to
QR

Scan QR to access full text

Cite this article
BibTeX
Citations
表12种不同金属材料的力学参数
科
Family		 属数
Number of
genus		 种数
Number of
species		 占总种数比例
Percentage of
total species (%)		 属
Genus		 种数
Number of
species		 占总种数比例
Percentage of total
species (%)
鹅膏菌科Amanitaceae 2 11 5.26 鹅膏菌属 Amanita 10 4.78
小菇科 Mycenaceae 2 12 5.74 丝盖伞属 Inocybe 5 2.39
多孔菌科 Polyporaceae 8 14 6.70 蜡蘑属 Laccaria 5 2.39
红菇科 Russulaceae 3 23 11.00 小皮伞属 Marasmius 6 2.87
小菇属 Mycena 11 5.26
光柄菇属 Pluteus 5 2.39
红菇属 Russula 17 8.13
栓菌属 Trametes 5 2.39
关闭全屏
  • BibTeX
  • EndNote
  • RefWorks
  • TxT
Links
Articles
Latest Articles
Most Read
Collections
Updates
Events
News
Multimedia
About
About Us
Contact
No. 86 Xueyuan South Road, Haidian District, Beijing
100081
010-62199257
qkjq@cast.org.cn

Copyright © 2025 China Association for Science and Technology. All rights reserved. For all open access content, the relevant licensing terms apply.
Sponsored by the Office of the Leading Group for Cybersecurity and Informatization of CAST, and supported by Science and Technology Review Publishing House