MULTILEVEL inverters (MLIs) are increasingly being used in a wide range of industrial applications today. These applications include distributed generation systems, motor drive applications, FACTS applications, induction heating systems, UPS systems, etc [1]-[4]. This is due to their unique features, such as the ability to generate output voltage waveforms with better harmonic spectra, higher power handling capability, the ability to withstand lower electromagnetic interfaces (EMIs), and the capacity to operate at higher efficiency over classic two-level inverters [5].

Traditional MLIs, including cascaded H-bridge MLI (CHB-MLI), flying capacitor MLI (FC-MLI), and neutral point clamped MLI (NPC-MLI), are widely used in various industrial applications but face challenges in generating higher-level output voltage waveforms due to the numerous components involved. This abundance of components leads to increased system size, cost, and complexity. For example, NPC-MLI relies on clamping diodes and DC link capacitors, FC-MLI requires multiple capacitors, and CHB-MLI necessitates independent DC power sources. Both FC and NPC MLIs also suffer from capacitor voltage unbalancing issues [6].

Moreover, conventional MLIs lack inherent output voltage boosting capabilities, which are advantageous for raising the output voltage of low-magnitude renewable sources like photovoltaic systems to match standard load or grid-end voltage levels. Achieving the desired output voltage typically requires the inclusion of a back-end transformer or a front-end DC-to-DC converter. This additional component further increases the size, cost, and complexity of the conversion system [7],[8].

In recent years, significant research has focused on advancing the topology of MLIs and addressing capacitor voltage imbalances. Some studies have proposed reduced device count (RDC) MLIs to minimize component count [9],[10]. However, RDC MLIs lack the ability to boost output voltage. Complex control strategies and additional circuits have been developed to manage capacitor voltage imbalances in NPC-MLI and FC-MLI, resulting in increased costs, larger system size, and complexity [11],[12].

The modular multilevel converter (MMC) stands out as a widely adopted power converter in contemporary applications. It offers a superior and more competitive solution compared to traditional two-level voltage source converters, particularly in high voltage direct-current transmission systems. The MMC, distinguished from other multilevel topologies, offers seamless scalability and achieves near sinusoidal output voltage synthesis through the utilization of cascaded modules comprised of semiconductor switches and floating capacitors. The asymmetric MMCs employ modules featuring asymmetric capacitor voltages to achieve elevated voltage levels with a diminished number of switching devices [13]-[15]. Nevertheless, the MMC lacks inherent capabilities for output voltage boosting and self-balancing of capacitor voltages. To address these limitations, auxiliary circuits or intricate control algorithms are necessitated for maintaining the desired voltages across the floating capacitors. The integration of such auxiliary circuits or complex control algorithms contributes to increased size, cost, and overall complexity of the converter structure.

A distinct category of MLIs, known as switched capacitor MLIs (SCMLIs), has emerged. SCMLIs can generate boosted output voltage using capacitors while requiring fewer power supplies. Furthermore, SCMLIs eliminate the need for intricate control algorithms or auxiliary circuitry to maintain capacitor voltage balance [16],[17]. Recent literature reports numerous creative SCMLIs classified into single source-based and multiple source-based types. Among single source-based SCMLIs, two categories exist: extendable and non-extendable. Notably, the past few years have seen the emergence of pioneering single source-based extendable SCMLIs [18]-[28].[18] introduces an innovative single-source-based extendable SCMLI consisting of a fundamental SC unit with three switches and one capacitor. Multiple such units interconnect in a cascaded manner to achieve higher output voltage levels. However, this approach necessitates a significant number of switches and driver circuits, thereby increasing the inverter’s cost and complexity. Moreover, the inverter relies on an H-bridge circuit to generate both load voltage polarities, leading to an increase in the total standing voltage (TSV) and the maximum switch voltage stress (MSV) rating of the inverter.

In [19], a novel SC cell was introduced, featuring two switches, one diode, and one capacitor. These cells are sequentially linked to construct a generalized cell, forming the basis of a single source-based extendable SCMLI along with an H-bridge circuit. The H-bridge circuit used in this structure enhances the inverter’s TSV and MSV. Furthermore, achieving a high-quality output voltage waveform in the inverter requires several switches, drivers, diodes, and capacitors, resulting in increased inverter’s cost and complexity. Similarly, in [20], a novel SC cell is proposed, requiring only one switch, two diodes, and one capacitor. Several of these cells are cascaded to form the generalized cell. However, the construction of a single source-based extendable SCMLI necessitates an H-bridge circuit at the load end, which also enhances the inverter’s TSV and MSV. In [21], a step-up switched capacitor converter (SCC) is proposed, forming the basis of a single source-based extendable SCMLI along with an H-bridge circuit. Notably, the capacitors in this structure can be charged in a binary asymmetrical pattern, enhancing the inverter’s boosting factors and output voltage levels. Nevertheless, this structure is susceptible to higher switch voltage stress and TSV. Similarly, a single source-based SCC with reduced components has been proposed in [22]. However, the converter requires an H-bridge circuit for generating both voltage polarities at the load end. This H-bridge requirement enhances the MSV and TSV of the structure. Furthermore, as the output voltage level enhances, the structure suffers from high switch voltage stress for some of the switches in the SCC circuit.

In recent years, innovative single source-based extendable SCMLIs have emerged, eliminating the need for an H-bridge circuit. An innovative H-bridge-free single source-based extendable SCMLI was proposed in [23], offering reduced MSV and TSV compared to similar structures. However, achieving higher output voltage levels still requires numerous switching devices, driver circuits, and capacitors. Despite its favorable TSV and MSV characteristics, the elevated component count limits its suitability for achieving higher voltage levels.[24] introduces a novel single source-based extendable SCMLI configuration, distinct from the traditional use of an H-bridge circuit. This structure employs a unique binary asymmetrical capacitor charging technique, resulting in an increased boosting factor. This enables the generation of higher output voltage levels while reducing the need for additional switching devices. However, it’s essential to note that certain switches in this innovative structure experience elevated voltage stress due to the enhanced output voltage levels and boost factors.

Fig. 1 illustrates recently proposed single source-based extendable SCMLIs without H-bridge circuits.[25] presents an innovative $\mathrm{H}$-bridge-free single source-based extendable SCMLI as shown in Fig. 1(a). This structure charges two series-connected capacitors $\left({C}_{\mathrm{a}1}\right.$ and $\left.{C}_{\mathrm{b}1}\right)$ simultaneously, each reaching half of the source voltage. Consequently, the structure can attain more output voltage levels with smaller voltage steps by integrating additional SC cells, as depicted in Fig. 1(a). However, this results in a limited boosting factor due to the smaller voltage steps. Moreover, to achieve higher output voltage levels, the inverter requires multiple capacitors and diodes, significantly increasing the component cost per level per boosting factor. In [26], an innovative single source-based extendable SCMLI structure is proposed without utilizing an H-bridge circuit as depicted in Fig. 1(b). The capacitors in this design can be charged to the supply voltage level, reducing the inverter’s TSV and MSV. Nonetheless, achieving higher output voltage levels still requires multiple unidirectional and bidirectional switches, driver circuits, and capacitors, contributing to increased complexity and cost.

[27] introduced an innovative single-source-based SCMLI without an $\mathrm{H}$-bridge circuit as shown in Fig. 1(c), inspired by the Marx inverter. This structure achieves higher output voltages while reducing MSV and TSV. However, it cannot add the supply voltage to all the capacitor voltages. Furthermore, some capacitors (such as ${C}_{\mathrm{b}1}$ and ${C}_{\mathrm{b}2}$) in this structure have a passive role, enhancing the boosting factor by energizing other capacitors. Achieving high-quality voltage waveforms requires a substantial number of switches, driver circuits, diodes, and capacitors. Furthermore, a novel SCMLI was proposed in [28], depicted in Fig. 1(d). This variant eliminates the need for an H-bridge configuration and achieves even higher voltage levels while minimizing switch voltage stress and TSV. Nonetheless, it still requires a significant quantity of switching elements, driver circuits, and capacitors to realize enhanced voltage levels.

In summary, the key challenges in single source-based extendable SCMLIs include the need for larger components to achieve higher output voltage levels, high MSV and TSV in H-bridge circuit-based SCMLIs, and limitations in boosting output. This article introduces an innovative single source-based extendable SCMLI configuration that eliminates the need for an H-bridge circuit at the load end. This structure charges capacitors in a trinary asymmetrical pattern, enabling higher output voltage levels and a greater boosting factor with fewer components. This reduced component count results in a cost-effective, highly efficient, compact, and lightweight structure compared to similar structures.

The article is structured as follows: Section I presents the introduction, while Section II delves into the 19-level proposed SCMLI. Moving on to Section III, the generalized proposed SCMLI is discussed comprehensively. The modulation strategy for the proposed SCMLI is described in Section IV. Section $\mathrm{V}$ elucidates the optimal procedure for selecting capacitors. Section VI describes the power losses analysis of the proposed SCMLI. The inrush current analysis of the proposed SCMLI is presented in Section VII. A comparative analysis between the proposed SCMLI and alternative configurations is outlined in Section VIII. Section IX presents the experimental findings of the 19-level proposed SCMLI. Lastly, the conclusions and references are presented.

The generalized proposed SCMLI is depicted in Fig. 6. It comprises $n$ number of capacitor legs (CL#1 to CL#n). Each CL consists of 3 series-connected capacitors. Each capacitor of a CL is charged by the previous CL capacitors except CL#1. For example, ${C}_{\mathrm{a}3}$ of CL#3 is charged by capacitors of CL#2. With this charging process, the voltage across the capacitors of $i$ th CL can be represented by (1).

With these capacitor voltages, the number of output voltage level $\left({N}_{\mathrm{L}}\right)$, maximum output voltage $\left({v}_{\text{omax }}\right)$, and boosting factor (B)of the structure in terms of $n$ can be represented by (2) to (4). Furthermore, the number of required switches $\left({N}_{\mathrm{{sw}}}\right)$ or drivers $\left({N}_{\mathrm{{dr}}}\right)$, diodes $\left({N}_{\mathrm{{dio}}}\right)$, and capacitors $\left({N}_{\mathrm{{cap}}}\right)$ in terms of $n$ can be expressed by (5) to (7), respectively. The TSV of the structure is expressed in (8).

This section outlines the modulation strategy for the proposed 19-level SCMLI, opting for the half-height fundamental switching (HHFS) strategy for its advantages in reduced switching losses and implementation simplicity. HHFS employs nine positive and nine negative DC signals, compared with the reference sinusoidal signal. Fig. 7(a) illustrates this process for the positive half-cycle, triggering inverter switching when the reference signal reaches halfway between voltage levels.

Fig. 7(b) shows cases sub-circuit-I, responsible for comparing the reference signal with positive DC signals and processing the output through logical gates (AND, XOR, and NOT) to generate logic signals $\left({I}_{0}\right.$ to $\left.{I}_{9}\right)$ corresponding to voltage levels from $0{V}_{\text{in }}$ to $9{V}_{\text{in }}$. Similarly, sub-circuit-II (Fig. 7(b)) compares the reference signal with negative DC signals, resulting in logic signals $\left({I}_{00}\right.$ to $\left.{I}_{99}\right)$ corresponding to voltage levels from $0{V}_{\text{in }}$ to $- 9{V}_{\text{in }}$. To derive the inverter’s switching pulses, these logic signals from sub-circuits I and II are ORed together. The determination of which logic signals participate in realizing a specific switching signal is governed by the 19-level SCMLI switching table (Table I). Fig. 7(d)-(g) provides an illustration of the OR-ing operation generating some of the switching signals.

This section outlines the capacitor selection process for 19-level proposed SCMLI. For evaluating the optimum capacitor sizes, the largest discharge period (LDP) of the capacitor over the output voltage cycle needs to be evaluated. Fig. 7 displays the LDP for different capacitors utilized in the 19-level SCMLI under a half-height (HH) fundamental switching frequency modulation scheme [19].

According to Fig. 8, LDP for ${C}_{\mathrm{a}1}$ is $\left({{t}_{12}- {t}_{8}}\right)$ whereas the LDP for ${C}_{\mathrm{c}1}$ is $\left({{t}_{32}- {t}_{28}}\right)$. It can be evident from Fig. 8 that the $\left({{t}_{12}- {t}_{8}}\right)$ time is equal to the $\left({{t}_{32}- {t}_{28}}\right)$ time. Hence, the LDP of ${C}_{\mathrm{{al}}}$ and ${C}_{\mathrm{{cl}}}$ are the same. Similarly, the LDPs for ${C}_{\mathrm{a}2}$ and ${C}_{\mathrm{c}2}$ are the same and are equal to either $\left({{t}_{16}- {t}_{4}}\right)$ or $\left({{t}_{36}- {t}_{24}}\right)$ as shown in Fig. 8. The LDP for ${C}_{\mathrm{b}1}$ is equal to either $\left({{t}_{11}- {t}_{9}}\right)$ or $\left({{t}_{31}- {t}_{29}}\right)$. Similarly, the LDP for ${C}_{\mathrm{b}2}$ is either $\left({{t}_{13}- {t}_{7}}\right)$ or $\left({{t}_{33}- {t}_{27}}\right)$. During LDP, the capacitors release their accumulated energy toward the load. Hence, the capacitor discharging current is equal to the load current during LDP. The amount of charge released by the capacitors in 19-level SCMLI can be expressed by (9) and (10). Here, ${\Delta Q}{C}_{\mathrm{{al}}}$ (or ${\Delta Q}{C}_{\mathrm{{cl}}}$), and ${\Delta Q}{C}_{\mathrm{{bl}}}$ are the amount of charge released from ${C}_{\mathrm{{al}}}$ (or ${C}_{\mathrm{c}1}$) and ${C}_{\mathrm{b}1}$ respectively. Similarly, ${\Delta Q}{C}_{\mathrm{a}2}$ (or ${\Delta Q}{C}_{\mathrm{c}2}$), and ${\Delta Q}{C}_{\mathrm{b}2}$ are the amount of charge released from ${C}_{\mathrm{a}2}$ (or ${C}_{\mathrm{c}2}$) and ${C}_{\mathrm{b}2}$ respectively. The symmetry of the output voltage waveform can be used to find the limit of integration for (9) and (10). Where $T$ is the fundamental time period for the output voltage cycle.

Considering the inverter is supplied a resistive load(R), the expression for the amount of charge released from the utilized capacitors can be expressed by (11) to (14). Using the HHFS modulation scheme, the various times $\left({t}_{1}\right.$ to $\left.{t}_{9}\right)$ in a quarter cycle of output voltage cycle can be evaluated by (15). The optimum capacitance for the utilized capacitors in 19-level SCMLI under $R$-load can be evaluated by (16) and (17). Here, $\tau$ is the percentage capacitor voltage ripple under steady-state conditions and $f$ is the output voltage frequency. Based on (16) and (17), the variation of optimum capacitance for different capacitors is depicted in Fig. 9. The plots provide the variation of optimum capacitance for five $\tau$ values (5%,7%,10%,15%, and 20%) and load resistance variation range of ${50\Omega }$ to ${400\Omega }$. According to Fig. 9, the optimum capacitance value decreases as the $R$ increases for a particular $\tau$ value. Similarly, the optimum capacitance value decreases as the $\tau$ value increases for a particular value of $R$.

The power losses analysis of the proposed 19-level SCMLI structure is presented in this section. Conduction losses, capacitor voltage ripple losses, and switching losses are the main losses associated with SCMLI [19]. The method for evaluating the various losses for the proposed 19-level SCMLI is provided in the ensuing subsections.

One of the major challenges for the SCMLIs is the inrush currents present in the circuit. These inrush currents flow through the charging loops of the circuit. As the capacitors behave like short circuits at the start of the inverter, the inrush current becomes very high magnitude and flows through the switches, diodes, capacitors, and the source. Also, under steady-state conditions, whenever the capacitors enter into the charging state, the high inrush currents flow through the charging loop due to the low equivalent series resistance associated with the charging path. These high values of inrush current can damage the switches, diodes, capacitors and source’s life span.

As per the charging process of the proposed converter, simultaneous charging of capacitors for CL#1 and CL#2 happens. As per switching states, the capacitors ${C}_{\mathrm{a}1}$ and ${C}_{\mathrm{c}1}$ have more LDP than that for ${C}_{\mathrm{b}1}$ in CL#1, whereas ${C}_{\mathrm{a}2}$ and ${C}_{\mathrm{c}2}$ have more LDP than that for ${C}_{\mathrm{b}2}$ in CL#2. So the charging inrush current will be more when simultaneous charging of $\left({{C}_{\mathrm{{al}}},{C}_{\mathrm{{bl}}}}\right)$ or $\left({C}_{\mathrm{{cl}}}\right.$, ${C}_{\mathrm{c}2}$) will happen. So evaluation of inrush current due to capacitor charging for Fig. 2(a) or (c) is explained. The equivalent circuit for simultaneous charging of ${C}_{\mathrm{a}1}$ and ${C}_{\mathrm{a}2}$ can be redrawn in Fig. 10. By applying the Kirchhoff’s voltage law (KVL), the magnitude of the charging currents can be expressed by (12). To mitigate this inrush current, a small value of the inductor in the range of ${33\mu }\mathrm{H}$ to ${100\mu }\mathrm{H}$ can be connected in series with the source for soft charging of the capacitors [29].

where ${r}_{\mathrm{{eql}}}= {r}_{\mathrm{d}}+ {r}_{\mathrm{{el}}}+ {r}_{\mathrm{{on}}},{r}_{\mathrm{{eq}}2}= {r}_{\mathrm{d}}+ 3{r}_{\mathrm{{el}}}+ {r}_{\mathrm{{on}}}+ {r}_{\mathrm{e}2}$.

In this section, the proposed SCMLI (PT) has been compared with popular asymmetric MMC [13],[14] and with recently developed single-source-based extendable SCMLIs [19],[21],[22],[24]-[28]. The comparison covers various aspects, including output voltage levels, required components, active switches for the highest voltage levels $\left({N}_{\mathrm{p}}\right)$, active switches in the capacitor charging path $\left({N}_{\mathrm{p}}\right)$, boosting factor(B), maximum capacitor voltage (MCV), maximum switch voltage stress (MSV), per unit TSV (TSV ${}_{\mathrm{{pu}}}$ i.e., total TSV per maximum output voltage), and the necessity of an H-bridge for negative voltage generation.

Table IV quantitatively compares PT with asymmetric MMCs and similar SCMLIs. The asymmetric MMCs presented in [13].[14] required significantly higher number of switching devices and driver circuits for generating higher output voltage levels. Furthermore, they do not provide any boosting feature and self-capacitor voltage balancing ability as compared to PT. As compared to SCMLIs, PT requires fewer switches compared to most of the suggested SCMLIs. For 19-level output voltage, PT uses only 12 switches, while [19],[22],[26] require 20 or more switches. Similarly, for 21-level output voltage,[27] and [28] use 20 switches, while PT uses only 12 for 19-level output. In terms of driver circuits, PT requires fewer than most topologies in Table IV. For diodes and capacitors, PT also demands fewer compared to the presented SCMLIs.

In comparing ${N}_{\mathrm{p}}$ and ${N}_{\mathrm{p}\_ \mathrm{c}}$, PT needs only 4 conducting switches to achieve the highest voltage level, and 2 conducting semiconductor devices to charge capacitors, both of which are lower than most suggested SCMLIs in Table IV. These lower ${N}_{\mathrm{p}}$ and ${N}_{\mathrm{p}}$ values in PT enhance the highest output voltage level, consequently improving the boosting factor of the inverter.

Referring to Table IV, PT achieves a maximum boosting factor for a 19-level output voltage waveform, akin to most suggested SCMLIs. Moreover, PT delivers a notably higher boosting factor compared to the SCMLI in [25]. In terms of ${TS}{V}_{\mathrm{{pu}}}$, PT yields lower values than [19],[21],[22],[26],[28] due to the absence of an $\mathrm{H}$-bridge. Table IV also presents a comparison of MCV and MSV. PT’s MCV is $3{V}_{\text{in }}$, while the MSV is $9{V}_{\text{in }}$ for realizing 19-level output voltage levels.

In the cost function (CF) comparison, a standard CF comprising component count and TSV components is outlined in (28). In this equation, $\alpha$ represents the weightage factor for TSV. When $\alpha > 1$, TSV carries more weight; when $\alpha < 1$, component count has more weight. The topologies have been compared for $\alpha$ values of 0.5 and 1 . According to Table IV, ${PT}$ demonstrates lower CF per level per boosting factor (CF/ $\left({{N}_{\mathrm{L}}\times B}\right))$ values for both $\alpha ={0.5}$ and $\alpha = 1$, outperforming most suggested SCMLIs and asymmetric MMCs.

Additionally, PT has been compared with [19],[22],[24],[26]-[28] across various output voltage levels, as shown in Fig. 11.

Table IV also presents generalized parameter expressions in terms of ${N}_{\mathrm{L}}$ for PT and the suggested SCMLIs. Fig. 11(a) illustrates semiconductor device requirements (sum of switches and diodes) versus the output voltage level for PT and the suggested structures. Notably, PT requires significantly fewer semiconductor devices for a given output voltage level compared to [19],[22],[26]-[28]. Nevertheless, PT exhibits a slightly greater number of semiconductor devices compared to [24]. Fig. 11(b) shows the capacitor requirement across a range of output voltage levels, highlighting that PT necessitates the fewest capacitors compared to the suggested SCMLIs. Fig. 11(c) displays the variation of TSV concerning ${N}_{\mathrm{L}}$ for all compared topologies. PT exhibits lower TSV than [22],[19],[28] but higher TSV than [24],[26],[27]. In Fig. 11(d), the variation of ${CF}$ per level (${CF}$/${N}_{\mathrm{L}}$) with output voltage level is shown. PT achieves significantly lower ${CF}/{N}_{\mathrm{L}}$ compared to [19],[22],[26]-[28].Nonetheless, PT exhibits a marginally higher ${CF}/{N}_{\mathrm{L}}$ value in comparison to the topology outlined in [24].

To experimentally validate the proposed SCMLI, a 19-level prototype was constructed, as depicted in Fig. 12. IRF640 MOSFETs(18A,200V)were employed as switching devices for the switches ${\mathrm{S}}_{\mathrm{b}1},{\mathrm{\;S}}_{\mathrm{c}1},{\mathrm{\;S}}_{\mathrm{b}2},{\mathrm{\;S}}_{\mathrm{c}2},{\mathrm{\;S}}_{\mathrm{p}}$, and ${\mathrm{S}}_{\mathrm{q}}$ whereas ${\mathrm{S}}_{\mathrm{a}1},{\mathrm{\;S}}_{\mathrm{d}1},{\mathrm{\;S}}_{\mathrm{a}2}$, and ${\mathrm{S}}_{\mathrm{d}2}$ have been implemented by IRF640 in series with a diode (MUR 460). For ${\mathrm{S}}_{\mathrm{r}}$ and ${\mathrm{S}}_{\mathrm{s}}$, IRF840 MOSFETs (8 A, 500 V) were chosen due to their higher voltage stress requirements. The inverter operated with a 31V input voltage. Capacitance values of ${2500\mu }\mathrm{F}$ each were selected for ${C}_{\mathrm{{al}}},{C}_{\mathrm{b}1}$, and ${C}_{\mathrm{c}1}$, while ${C}_{\mathrm{a}2},{C}_{\mathrm{b}2}$, and ${C}_{\mathrm{c}2}$ were equipped with ${1880\mu }\mathrm{F}$ each.

Fig. 13(a) shows the 19-level output voltage $\left({{v}_{\mathrm{o}}\left( t\right)}\right)$ along with the load current $\left({{i}_{\mathrm{o}}\left( t\right)}\right)$ when the inverter supplies a resistive load (R)of ${120\Omega }$. As per this figure, the peak ${v}_{\mathrm{o}}\left( t\right)$ is 240V, whereas the peak ${i}_{\mathrm{o}}\left( t\right)$ is 2A. The ${v}_{\mathrm{o}}\left( t\right)$ waveform has 19 voltage steps and it is in-phase with ${i}_{\mathrm{o}}\left( t\right)$. With the same load, the steady state capacitor voltage waveform with ${v}_{\mathrm{o}}\left( t\right)$ and ${i}_{\mathrm{o}}\left( t\right)$ is depicted in Fig. 13(b)-(d). Fig. 13(d) shows the voltage across the capacitors ${C}_{\mathrm{{cl}}}$, and ${C}_{\mathrm{b}1}$ whereas Fig. 13(c) depicts the voltage profiles for ${C}_{\mathrm{a}1}$ and ${C}_{\mathrm{c}2}$. As per these figures, the voltage across ${C}_{\mathrm{c}1}$ and ${C}_{\mathrm{a}1}$ are 28V each whereas that for ${C}_{\mathrm{b}1}$ is 26V. Also, the voltage across ${C}_{\mathrm{a}2}$ and ${C}_{\mathrm{c}2}$ are equal to 77V each whereas the voltage across ${C}_{\mathrm{b}2}$ is equal to 75V as shown in Fig. 13(d). According to Fig. 13, the capacitor voltages are balanced and stable with the switching states as described in Table I. The experimental boosting factor of the structure is $\left({{240}/{31}}\right)= {7.74}$ which is lower than the theoretical boosting factor $\left({B = 9}\right)$ due to the voltage drops in the parasitic resistances in the current flow paths.

Under the same load condition, the voltage stresses of various switches are observed and depicted in Fig. 14. Fig. 14(a) presents the voltage stresses of ${\mathrm{S}}_{\mathrm{{al}}},{\mathrm{S}}_{\mathrm{{bl}}},{\mathrm{S}}_{\mathrm{{cl}}}$, and ${\mathrm{S}}_{\mathrm{{dl}}}$. As per this figure, the voltage stresses across ${\mathrm{S}}_{\mathrm{{a1}}}$ and ${\mathrm{S}}_{\mathrm{{d1}}}$ are bipolar, whereas the voltage stresses for ${\mathrm{S}}_{\mathrm{b}1}$ and ${\mathrm{S}}_{\mathrm{c}1}$ are unipolar. In addition, the peak stress voltages incurred in ${\mathrm{S}}_{\mathrm{{al}}}$ and ${\mathrm{S}}_{\mathrm{{dl}}}$ are within ${31}\mathrm{\;V}$, whereas the peak stress voltages for ${\mathrm{S}}_{\mathrm{b}1}$ and ${\mathrm{S}}_{\mathrm{c}1}$ are within ${61}\mathrm{\;V}$. Similarly, Fig. 14(b) and (c) depicts the voltage stress profiles for ${\mathrm{S}}_{\mathrm{a}2},{\mathrm{\;S}}_{\mathrm{b}2},{\mathrm{\;S}}_{\mathrm{c}2}$, and ${\mathrm{S}}_{\mathrm{d}2}$. As per these figures, the voltage stresses across ${\mathrm{S}}_{\mathrm{a}2}$ and ${\mathrm{S}}_{\mathrm{d}2}$ are bipolar, whereas the voltage stresses for ${\mathrm{S}}_{\mathrm{b}2}$ and ${\mathrm{S}}_{\mathrm{c}2}$ are unipolar. Further, the peak stress voltages across ${\mathrm{S}}_{\mathrm{a}2}$ and ${\mathrm{S}}_{\mathrm{d}2}$ are within ${85}\mathrm{\;V}$, whereas the peak stress voltages across ${\mathrm{S}}_{\mathrm{b}2}$ and ${\mathrm{S}}_{\mathrm{c}2}$ are within ${160}\mathrm{\;V}$. Fig. 14(d) shows the voltage stress profiles for ${S}_{p}$ and ${S}_{r}$. As per this figure, the peak stress voltage for ${\mathrm{S}}_{\mathrm{p}}$ is within ${31}\mathrm{\;V}$, whereas the peak stress voltage for ${\mathrm{S}}_{\mathrm{r}}$ is within ${240}\mathrm{\;V}$. The experimental TSV of the proposed 19-level SCMLI is ${1191}\mathrm{\;V}$. Considering the same load condition, the current profiles for ${C}_{\mathrm{{al}}},{C}_{\mathrm{{bl}}}$ and ${C}_{\mathrm{{cl}}}$ are depicted in Fig. 15(a). The capacitor currents are pulsating in nature due to the charging state of the capacitors. The maximum peak current passing through ${C}_{\mathrm{{al}}},{C}_{\mathrm{{bl}}}$ and ${C}_{\mathrm{{cl}}}$ are within 10 A. Similarly, the current profiles for ${C}_{\mathrm{a}2},{C}_{\mathrm{b}2}$, and ${C}_{\mathrm{c}2}$ have been observed, and the peak current passing through ${C}_{\mathrm{a}2},{C}_{\mathrm{b}2}$ and ${C}_{\mathrm{c}2}$ are within 20A.

For verifying the performance of the 19-level structure under the $R - L$ load condition, the inverter supplies an $R - L$ load of ${120\Omega }$ and ${50}\mathrm{{mH}}$. The ${v}_{\mathrm{o}}\left( t\right)$ and ${i}_{\mathrm{o}}\left( t\right)$ under this load condition are observed as depicted in Fig. 15(b). According to this figure, the ${i}_{\mathrm{o}}\left( t\right)$ is lagging behind ${v}_{\mathrm{o}}\left( t\right)$. Under the resistive load of 120 $\Omega$, the FFT analysis of the experimental ${v}_{\mathrm{o}}\left( t\right)$ is shown in Fig. 16(a). According to this figure, the output voltage waveform has a 234 V peak fundamental component with a voltage THD of 5.05%. Similarly, the FFT analysis of ${i}_{\mathrm{o}}\left( t\right)$ is shown in Fig. 16(b). As per this figure, the peak value of fundamental current is 1.87 A with a current THD of 4.49%.

The proposed 19-level SCMLI has three types of power losses, namely conduction losses, capacitor voltage ripple losses, and switching losses. Fig. 17 depicts the proportion of various losses in the 19-level inverter. As the inverter has been switched using a low switching frequency modulation strategy, the switching losses in the structure with a resistive load of 120 $\Omega$ are negligible(0.02W). The conduction and ripple losses in the inverter are ${3.3}\mathrm{\;W}$ and ${6.8}\mathrm{\;W}$, respectively. From FFT analysis, the output power of the inverter for ${120\Omega }$ load is 219 W. The total loss of the inverter is ${10.12}\mathrm{\;W}$. The experimental efficiency of the proposed inverter is 95.6%.

This paper proposes a novel single-source-based SCMLI structure. The structure can realize higher output voltage levels with a lower number of components such as switches, and capacitors. It also provides a higher boosting factor. In addition, it can be easily extended for higher voltage level generation. The absence of an H-bridge circuit makes the TSV of the structure lower than other similar SCMLIs. The paper discusses the circuit description, charging process, and operating principle for the 19-level proposed SCMLI. Also, the generalized structure has been developed. A detailed discussion of the modulation strategy, the optimum capacitor selection procedure, and power loss analysis have been presented. Further, the paper presents the current evaluation and its mitigation. An extensive comparison study shows that the proposed inverter is more cost-effective than most of the recently developed similar SCMLIs for a range of output voltage levels. The performances of the proposed SCMLI have been verified by an extensive experimental study of the 19-level proposed SCMLI. For an output power of 219 W, the 19-level SCMLI provides 96.5% efficiency.