A New 7, 15 and 31-level Modular Reduced Switch Multilevel Inverter With Gating Signal Generation Using Digital Output Pins

A New 7, 15 and 31-level Modular Reduced Switch Multilevel Inverter With Gating Signal Generation Using Digital Output Pins

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Amit V. SANT, Kashyap PATOLIYA

CPSS Transactions on Power Electronics and Applications | 2024, 9(4) : 373 - 383

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CPSS Transactions on Power Electronics and Applications | 2024, 9(4): 373-383

• Original articles •

A New 7, 15 and 31-level Modular Reduced Switch Multilevel Inverter With Gating Signal Generation Using Digital Output Pins

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Amit V. SANT, Kashyap PATOLIYA

Affiliations

Pandit Deendayal Energy University Department of Electrical Engineering, School of Energy Technology Gandhinagar India

Amit V. Sant received his Ph.D. (Electrical Engineering) degree from the Indian Institute of Technology Delhi, New Delhi, India. Prior to that, he completed his Bachelor's degree in Electrical and Electronics Engineering and Master's Degree in Power Apparatus and Systems from Manipal Institute of Technology, Manipal, Karnataka, India, and Nirma University, Ahmedabad, India, respectively. From 2012 to 2014, he was a post-doctoral researcher at Masdar Institute of Science and Technology, Masdar, City, Abu Dhabi, UAE. He joined the Electrical Engineering Department, Babaria Institute of Technology as an Assistant Professor in 2015. In April 2016, he joined the Department of Electrical Engineering, Pandit Deendayal Energy University, as an Assistant Professor, where he became an Associate Professor in 2021. His present research focuses on multilevel inverters, z-source inverters, high gain DC-DC converters, grid integration of renewables, charging infrastructure for electric vehicles, power quality enhancement, smart metering, and applications of AI/ML in power electronics.

Kashyap Patoliya received his Bachelor's of Technology degree in Electrical Engineering from Pandit Deendayal Energy University, Gandhinagar, India in 2023. His research interests include multilevel inverters, DC-DC converters, control of grid tied inverters, and power system stability analysis.

Published: 2024-12-10 doi: 10.24295/CPSSTPEA.2024.00018

Outline

Abstract

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This paper proposes a reduced switch modular multilevel inverter (RSMMLI) requiring eight, thirteen, and fifteen switches per phase for 7level, 15level, and 31level output voltages, respectively. For the generation of 7level, 15level, and 31level output voltages, the proposed MLI employs two, three, and four designed modules, each comprising switches, diodes, and a DC source, respectively. The interconnection of modules results in the generation of unipolar staircase voltage. Further, an Hbridge inverter (HBI) facilitates DCAC conversion. With modular construction, the levels can be easily increased in the proposed topology by adding extra modules. The merits of the proposed topology are highlighted through a comparative analysis. The higher switch count in MLI necessitates the use of multiple digital signal processors (DSPs), thereby complicating the gating circuitry. To simplify the gating requirements, this paper utilizes the digital output pins in a DSP, which are far higher in number than the PWM pins, for gate pulse generation. This negates the needs of multiple DSPs. The operation of the developed experimental prototype of the proposed 7level, 15level, and 31level RSMMLI, controlled through the digital output pins of a DSP, is analyzed for steadystate and dynamic conditions.

Key words

Inverters / modular / multi-level inverters / reduced switch count

Cite this Article

Amit V. SANT, Kashyap PATOLIYA. A New 7, 15 and 31-level Modular Reduced Switch Multilevel Inverter With Gating Signal Generation Using Digital Output Pins[J]. CPSS Transactions on Power Electronics and Applications, 2024 , 9 (4) : 373 -383 . DOI: 10.24295/CPSSTPEA.2024.00018

Full Text

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I. Introduction

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MULTI-LEVEL inverters (MLIs) find extensive usage in medium voltage drives, high voltage DC transmission systems, flexible AC transmission systems, and grid integration of renewable energy systems [1],[2]. Recently, MLIs have also been reported for low-power applications [3]. Generally, MLIs comprise of multiple power semiconductor switches, DC source/s, and capacitors. The distinguishing feature of MLI is the availability of output AC voltage with more than two levels. With the increase in voltage levels, the total harmonic distortion (THD) of voltage and current at the inverter output is reduced. Additionally, MLI offers the advantages of reduced voltage stress on switches, lower $\mathrm{d}v/\mathrm{d}t$ and electromagnetic interference, and switching frequency lesser than that encountered in 2-level inverters [4].

The three basic MLI topologies are:(i) neutral point clamped (NPC) inverter,(ii) flying capacitor (FC) inverter, and (iii) cascaded H-bridge inverter (HBI)[4]. In MLIs, with an increase in output voltage levels, the number of switches and other components (diodes, DC sources and capacitors) also increase. All three topologies necessitate(2n - 2)switches/ phases for n -levels of output voltage. Moreover, clamping diodes are needed in NPC-MLI, and additional capacitors are necessary for FC-MLI. The use of additional capacitors results in increased cost and a challenge for voltage balancing. These traditional topologies need more switches for generating higher voltage levels and consequent increase in circuit complexity, requirement of gate drivers, heat sinks and protection units [5].

Reduced switch count (RSC) MLI topologies have drawn significant attention as they can overcome the demerits of increased switch count associated with the three basic MLI topologies. The evolution of RSC-MLI from a theoretical concept to practical realization is due to reduced switch count and gate driver requirements, increased efficiency and low cost [6]. A detailed survey on RSC-MLI topologies is presented by Vemuganti et al [6]. Different RSC-MLI topologies reported in the literature are modular RSC-MLI [7]-[9], transformer-based RSC-MLI [10], transformer-less RSC-MLI [11], single source RSC-MLI [12], multiple source RSC-MLI [13] unit based RSC-MLI [14], etc. Among these MLI topologies, modular RSC-MLI has gained significant interest due to the additional merits of high modularity and fault-ride-through capability [15]. Moreover, with modularity, the output voltage levels can be easily increased by adding additional modules or units.

Modular RSC-MLI with and without HBI are reported in [16]-[18]. Topologies with H-bridge feature a straightforward and cost-effective construction, providing 2n+1 levels for n levels [16]. Further, modular RSC-MLIs with single and multiple DC sources are also reported [12],[17]. Switched capacitor-based RSC-MLI are reported in [19],[20], wherein capacitors are added instead of using multiple DC sources. Such topologies can implement voltage boost action with capacitor switching [19]. This may eliminate the need for a step-up transformer [21]. Moreover, these topologies have self-balancing capability. However, SC-MLIs have the following drawbacks.

(a) Modulation complexity, complicated control schemes, increased switching losses, and requirement of higher capacitance [22].

(b) Difficulty in balancing capacitor size and voltage ripple impacts overall efficiency [23].

(c) The process of charging the capacitors in the fundamental units of switched-capacitor systems presents challenge in the form of significant surge in current. This abrupt increase in current, stresses the switches present in the charging path. Increased current stress can lead to wear and tear on switches, potentially reducing their operational lifespan and reliability [24].

(d) Soft start procedures/soft switching techniques can be helpful. However, as outlined in [24], it complicates system implementation. Also, realizing the soft switching technique for SC-MLIs is challenging.

(e) Practical implementations and applications, SC-MLI faces significant challenges in design, operation, and performance, primarily due to its reliance on capacitors, which complicates both design and operational aspects.

To tackle this problem, modular RSC-MLI topologies with multiple DC sources can be used, these topologies are reported [7]-[9]. Reference [7], presents an asymmetrical modular RSC-MLI made up of square T-Type modules. The module facilitates the generation of 17-level output voltage with twelve switches, of which six switches are utilized for forming three bidirectional switches, and three unequal DC sources. Another T-type topology, termed as cross switched T-Type topology, is described by Meraj et al [8]. The module facilitates the generation of 17-level output voltage with ten switches, of which four switches are utilized for forming three bidirectional switches, and three unequal DC sources. Samataei et al [9] have developed E-Type module for asymmetrical modular RSC-MLI, where each module can generate 13-level output voltage using ten switches and four unequal DC sources.

Packed U-cell (PUC) is another RSC-MLI topology reported in [25]-[27]. PUC-MLI utilizes only one DC source and necessitates voltage balancing for the capacitors employed. For 7-level output voltage, PUC-MLI employs a DC source, a capacitor, and six switches. Nonetheless, some inadequacies present in PUC-MLI are (a) not fully modular,(b) limited for the low power application,(c) higher switch rating, and (d) an increase in capacitor rating for extension of the topology [26].

In all MLI topologies, the increase in the number of levels is accompanied by a rise in the number of switches. Consequently, the number of pulse width modulated (PWM) gating signals increases. Generally, the digital signal processors (DSPs) used in power electronics applications have limited PWM pins. Multiple DSPs can be employed for the MLI, but it increases complexity and necessitates communication and synchronization between the DSPs involved.

This paper proposes a new modular 7-level, 15-level, and 31-level modular RSC-MLI topology with gate pulse generation using digital output pins of a DSP. Two different modules, made up of switches, diodes, and a DC source, are employed. With the help of a network of these modules, a unipolar staircase voltage is generated. An H-bridge inverter further performs DC-AC conversion on the staircase voltage. The PWM gating signal generation for the modules makes use of the DSP’s digital output pins, which are in substantially greater numbers. DC-AC conversion of unipolar staircase voltage is facilitated by an HBI. In HBI, a pair of diagonally opposite pins are ON during the positive half-cycle of output voltage. During the negative-half cycle, the alternate pair of switches is ON. In the proposed RSC-MLI topology, 7-level, 15-level, and 31-level output voltages are respectively generated with eight, thirteen, and fifteen switches per phase and two, three, and four modules per phase. Modular structure easily allows for level expansion. A detailed comparative analysis along with investigations on switch losses for the proposed RSC-MLI are also presented. Lastly, the proposed 7-level, 15-level, and 31-level RSC-MLI operations are validated through experimental studies.

The highlights of the proposed MLI topology are:(a) A new reduced switch modular multilevel inverter topology with the provision for 7, 15, and 31-level output voltage has been developed and its performance is validated experimentally.(b) The gate pulse generation for the proposed MLI has been implemented using general-purpose input output pins of TMS320F28335 DSP, instead of limited PWM pins.(c) The proposed MLI has the advantages of modular construction, absence of storage element, provision to bypass a module if any fault is developed, and thereby providing fault tolerant operation.(d) Assessment of power loss using equivalent circuits and mathematical equations is carried out.(e) A detailed comparative analysis reveals that the proposed MLI topology presents an optimal design with the balance between switch count and total standing voltage (TSV) requirement.

II. Proposed Modular RSC-MLI

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The power circuit configuration of the proposed RSC-MLI topology for one phase is illustrated in Fig. 1(a). The power circuit consists of (i) a staircase DC voltage generation (SDVG) unit, and (ii) HBI made up of ${\mathrm{S}}_{1}- {\mathrm{S}}_{11}$ and ${\mathrm{S}}_{2}- {\mathrm{S}}_{22}$. SDVG unit comprises of a network of modules with individual DC sources connected at the input terminals of the module. SDVG unit serves to provide unipolar staircase voltage across its output terminals, denoted by J and $K$. HBI, connected across J and $K$, performs the DC-AC conversion and thereby facilitates the availability of bipolar supply across the load.

SDVG circuit comprises of modules x and Y. Depending on the output voltage levels, the number of modules x and Y in SDVG unit varies. Fig. 1(b) shows the internal circuit configuration of module x and Y. Each of these modules comprises of two switches and a diode. Considering that A represents the module number, Module ${\mathrm{X}}_{A}$ comprises of upper switch, ${\mathrm{X}}_{\mathrm{{UX}}A}$, lower switch, ${\mathrm{S}}_{\mathrm{{LX}}A}$, diode, ${\mathrm{D}}_{\mathrm{X}A}$, two input terminals, ${\mathrm{H}}_{\mathrm{{TX}}A}$ and ${\mathrm{H}}_{\mathrm{{BX}}A}$, and three output terminals, ${\mathrm{C}}_{\mathrm{{TX}}A}$, ${\mathrm{C}}_{\mathrm{{MX}}A}$, and ${\mathrm{C}}_{\mathrm{{BX}}A}$. In module x, two connections are provided at ${\mathrm{H}}_{\mathrm{{BX}}A}$. Connection of ${\mathrm{C}}_{\mathrm{{BX}}A}$ at ${\mathrm{H}}_{\mathrm{{BX}}A}$ facilitates the connection of DC source of the lower connected module in series with ${V}_{\mathrm{X}A}$. While the connection of ${\mathrm{C}}_{\mathrm{{MX}}A}$ to ${\mathrm{H}}_{\mathrm{{BX}}A}$ through ${\mathrm{D}}_{\mathrm{X}A}- {\mathrm{S}}_{\mathrm{{LX}}A}$ is utilized to bypass the lower connected module. ${S}_{\mathrm{{UX}}A}$ is used to make use of ${V}_{\mathrm{X}A}$.

Similarly, Module ${\mathrm{Y}}_{A}$, where $A$ represents the module number, comprises of upper switch, ${\mathrm{S}}_{\mathrm{{UY}}A}$, lower switch, ${\mathrm{S}}_{\mathrm{{LY}}A}$, diode, ${\mathrm{D}}_{\mathrm{Y}A}$, two input terminals, ${\mathrm{H}}_{\mathrm{{TY}}A}$ and ${\mathrm{H}}_{\mathrm{{BY}}A}$, and three output terminals, ${\mathrm{C}}_{\mathrm{{TY}}A},{\mathrm{C}}_{\mathrm{{MY}}A}$ and ${\mathrm{C}}_{\mathrm{{BY}}A}$. In module Y, two connections are provided at ${\mathrm{H}}_{\mathrm{{TY}}A}$. ${\mathrm{S}}_{\mathrm{{UY}}A}$ connecting ${\mathrm{H}}_{\mathrm{{TY}}A}$ to ${\mathrm{C}}_{\mathrm{{TY}}A}$ facilitates provision for series connection of ${V}_{\mathrm{Y}A}$ with ${V}_{\mathrm{X}A}$. The connection of ${\mathrm{H}}_{\mathrm{{TY}}A}$ at ${\mathrm{C}}_{\mathrm{{MY}}A}$ through ${\mathrm{S}}_{\mathrm{{LY}}A}- {\mathrm{D}}_{\mathrm{Y}A}$ is utilized to bypass module $X$.

In case of the modules, subscripts $\mathrm{L}$ and $\mathrm{U}$ respectively indicate lower and upper, whereas subscripts $\mathrm{T},\mathrm{M}$ and $\mathrm{B}$ correspondingly represent top, middle and bottom. SDVG formed with the cascade connection of one or multiple x and Y modules. As mentioned earlier, the number of x and Y modules in the MLI depend on the required levels of output AC voltage. If the output voltage of SDVG has n levels then the output of HBI has $\left({{2n}+ 1}\right)$ levels. The power circuit configuration of SDVG for 7-level, 15-level, and 31-level modular RSC-MLI are shown in Figs. 2 and 3. In the following sub-sections, the operation of the proposed MLI is demonstrated and analyzed for output AC voltage with 7-level, 15-level, and 31-level.

A. Description of the Proposed 7-Level Modular RSC-MLI

Fig. 2(a) shows the power circuit configuration for the proposed 7-level modular RSC-MLI made up of cascade connection of modules ${\mathrm{X}}_{1}$ and ${\mathrm{Y}}_{1}.{V}_{\mathrm{X}1}$ and ${V}_{\mathrm{Y}1}$ are the DC sources connected across ${\mathrm{H}}_{\mathrm{{TX}}1}- {\mathrm{H}}_{\mathrm{{BX}}1}$ and ${\mathrm{H}}_{\mathrm{{TY}}1}- {\mathrm{H}}_{\mathrm{{BY}}1}$, which are the input terminals for module ${\mathrm{X}}_{1}$ and ${\mathrm{Y}}_{1}$, respectively. At the output of SDVG, ${\mathrm{C}}_{\mathrm{{TXl}}}- {\mathrm{C}}_{\mathrm{{MXl}}}- {\mathrm{C}}_{\mathrm{{BXl}}}$ of module ${\mathrm{X}}_{1}$ are respectively connected to ${\mathrm{C}}_{\mathrm{{MY}}1}- {\mathrm{C}}_{\mathrm{{BY}}1}- {\mathrm{C}}_{\mathrm{{TY}}1}$ module ${\mathrm{Y}}_{1}$. The interconnection of ${\mathrm{C}}_{\mathrm{{TXI}}}- {\mathrm{C}}_{\mathrm{{MYI}}}$ and ${\mathrm{C}}_{\mathrm{{MXI}}}- {\mathrm{C}}_{\mathrm{{BYI}}}$ form the positive and negative terminals of SDVG, respectively indicated as terminals J and $K$. The switching table for this topology is shown in Table I, where ${V}_{\text{SUX1 }}- {V}_{\text{SLX1 }}- {V}_{\text{SUY1 }}- {V}_{\text{SLY1 }}$ are the corresponding voltages across switches ${\mathrm{S}}_{\mathrm{{UX}}1}- {\mathrm{S}}_{\mathrm{{LX}}1}- {\mathrm{S}}_{\mathrm{{UY}}1}- {\mathrm{S}}_{\mathrm{{LY}}1}$. When ${\mathrm{S}}_{\mathrm{{UX}}1}- {\mathrm{S}}_{\mathrm{{LX}}1}$ are $\mathrm{{ON}}$, ${V}_{JK}= {V}_{\mathrm{X}1}$. Alternately, ${V}_{JK}= {V}_{\mathrm{Y}1}$ when only ${\mathrm{S}}_{\mathrm{{LY}}1}$ is $\mathrm{{ON}}$ and ${V}_{JK}= \left({{V}_{\mathrm{X}1}+ {V}_{\mathrm{Y}1}}\right)$, the peak DC voltage, when ${\mathrm{S}}_{\mathrm{{UX}}1}- {\mathrm{S}}_{\mathrm{{UY}}1}$ are ON. With all the switches of module turned OFF, ${V}_{JK}= 0$. This holds true for the proposed topology for all levels. ${V}_{JK}$ is a DC staircase voltage applied at the input terminals of HBI. With only ${\mathrm{S}}_{1}- {\mathrm{S}}_{11}$ of HBI ON, AC voltage levels of (V_Xl), (V_Yl) and (V_Xl)+(V_Yl) are obtained. When only ${\mathrm{S}}_{2}- {\mathrm{S}}_{22}$ of HBI are $\mathrm{{ON}},- {V}_{\mathrm{X}1}$, $-{V}_{\mathrm{Y}1}$ and $-\left({{V}_{\mathrm{X}1}+ {V}_{\mathrm{Y}1}}\right)$ are obtained at the output.

B. Description of the Proposed 15-Level Modular RSC-MLI

Fig. 2(b) demonstrates the power circuit configuration for the proposed 15-level modular RSC-MLI made up with the addition of module ${\mathrm{X}}_{2}$ to cascade connection of modules ${\mathrm{X}}_{1}$ and ${\mathrm{Y}}_{1}$. In addition to ${V}_{\mathrm{X}1}$ and ${V}_{\mathrm{Y}1}$, a third DC source ${V}_{\mathrm{X}2}$ is included in the circuit. ${V}_{\mathrm{X}2}$ is connected across the input terminals of ${\mathrm{X}}_{2},{\mathrm{H}}_{\mathrm{{TX}}2}- {\mathrm{H}}_{\mathrm{{BX}}2}$. At the output side of SDVG, terminals ${\mathrm{C}}_{\mathrm{{TX}}1}$ is connected to ${\mathrm{C}}_{\mathrm{{TX}}2}$ through a series connection of diode ${\mathrm{D}}_{\mathrm{U}}$ and switch ${\mathrm{S}}_{\mathrm{U}}.{\mathrm{C}}_{\mathrm{{BY}}1}$ is directly connected to ${\mathrm{C}}_{\mathrm{{TX}}2}$. ${\mathrm{C}}_{\mathrm{{TX}}1}$ forms the positive terminal of SDVG, denoted as terminal J. Similarly, ${\mathrm{C}}_{\mathrm{{MX}}1}- {\mathrm{C}}_{\mathrm{{BY}}1}$ are connected to ${\mathrm{C}}_{\mathrm{{BX}}2}$ through the series connection of switch ${\mathrm{S}}_{\mathrm{L}}$ and diode ${\mathrm{D}}_{\mathrm{L}}$. In this topology, ${\mathrm{C}}_{\mathrm{{MX}}2}$ forms the negative terminal SDVG, denoted by $K$. Moreover, from Fig. 2(b), it can also be observed that ${\mathrm{C}}_{\mathrm{{BX}}1}- {\mathrm{C}}_{\mathrm{{TY}}1}$ are interconnected. ${\mathrm{S}}_{\mathrm{U}}$ and ${\mathrm{S}}_{\mathrm{L}}$ are specifically included to bypass a particular module. For example, when ${V}_{JK}= {V}_{\mathrm{X}1}$ is to be implemented switch ${\mathrm{S}}_{\mathrm{L}}$ is turned $\mathrm{{ON}}$ so that ${V}_{\mathrm{X}2}$ and ${V}_{\mathrm{Y}1}$ are not included in the circuit. Similarly, ${\mathrm{S}}_{\mathrm{U}}$ is useful as turning it ON can result in the exclusion of ${V}_{\mathrm{X}1}$ and ${V}_{\mathrm{Y}1}$ from the circuit. By controlling the gate pulses to module ${\mathrm{X}}_{2},{V}_{JK}= {V}_{\mathrm{X}2}$ can be obtained. With all the switches of the three modules turned OFF, ${V}_{JK}= 0$. The diodes, ${\mathrm{D}}_{\mathrm{L}}$ and ${\mathrm{D}}_{\mathrm{U}}$ ensure that the antiparallel diode of ${\mathrm{S}}_{\mathrm{U}}$ and ${\mathrm{S}}_{\mathrm{L}}$ do not conduct, and thereby prevent any undesirable operation. The switching table for this topology is displayed in Table II, where ${V}_{\mathrm{{SUX}}1}$ -${V}_{\mathrm{{SLX}}1}- {V}_{\mathrm{{SUY}}1}- {V}_{\mathrm{{SLY}}1}- {V}_{\mathrm{{SUX}}2}- {V}_{\mathrm{{SLX}}2}- {V}_{\mathrm{{SU}}}- {V}_{\mathrm{{SL}}}$ are the corresponding voltages across switches ${\mathrm{S}}_{\mathrm{{UX}}1}- {\mathrm{S}}_{\mathrm{{LX}}1}- {\mathrm{S}}_{\mathrm{{UY}}1}- {\mathrm{S}}_{\mathrm{{LY}}1}- {\mathrm{S}}_{\mathrm{{UX}}2}- {\mathrm{S}}_{\mathrm{{LX}}2}- {\mathrm{S}}_{\mathrm{U}}-$${\mathrm{S}}_{\mathrm{L}}$. SDVG generates the voltage levels V_X1, V_Y1, V_X2, (V_X1+V_Y1), (V_Y1+V_X2),(V_X1+V_X2), and (V_X1+V_X2+V_Y1). For these voltage levels, HBI correspondingly generates AC voltage with the levels of $\pm {V}_{\mathrm{X}1},\pm {V}_{\mathrm{Y}1},\pm {V}_{\mathrm{X}2},\pm \left({{V}_{\mathrm{X}1}+ {V}_{\mathrm{Y}1}}\right), \pm \left({{V}_{\mathrm{X}1}+ {V}_{\mathrm{X}2}}\right)$, $\pm \left({{V}_{\mathrm{Y}1}+ {V}_{\mathrm{X}2}}\right)$, and $\pm \left({{V}_{\mathrm{X}1}+ {V}_{\mathrm{X}2}+ {V}_{\mathrm{Y}1}}\right)$. Further, $0\mathrm{\;V}$ is generated when all the switches of the module network are OFF. In the proposed topology, the increase in levels of voltages from seven to fifteen comes at the cost of one additional module and switches ${\mathrm{S}}_{\mathrm{U}}$ and ${\mathrm{S}}_{\mathrm{L}}$.

C. Description of the Proposed 31-Level Modular RSC-MLI

The power circuit configuration for the proposed 31-level modular RSC-MLI is illustrated in Fig. 3. One of the distinguishing features is that a series connection of DC source ${V}_{\mathrm{Y}2}$ and switch ${\mathrm{S}}_{3\mathrm{Y}2}$ is connected across the input terminals ${\mathrm{H}}_{\mathrm{{TY}}2}$ -${\mathrm{H}}_{\mathrm{{BY}}2}$ of module ${\mathrm{Y}}_{2}$. At the output of SDVG, interconnection of ${\mathrm{C}}_{\mathrm{{TX}}1}- {\mathrm{C}}_{\mathrm{{MY}}1}$ is connected to that of ${\mathrm{C}}_{\mathrm{{MX}}1}- {\mathrm{C}}_{\mathrm{{BY}}1}- {\mathrm{C}}_{\mathrm{{MY}}2}$ through series connection of ${\mathrm{S}}_{\mathrm{U}}- {\mathrm{D}}_{\mathrm{U}}$. This interconnection forms the positive terminal of SDVG, indicated as terminal J. The negative terminal of SDVG, $K$, is formed by the interconnection of ${\mathrm{C}}_{\mathrm{{MX}}2}- {\mathrm{C}}_{\mathrm{{BY}}2}$.

In addition to the connections employed at the output side of SDVG in the proposed 15-level modular RSC-MLI, there exists an interconnection of ${\mathrm{C}}_{\mathrm{{BX}}2}$ with ${\mathrm{C}}_{\mathrm{{TY}}2}$. As per the switching table shown in Table II, at the output of SDVG unit the possible voltage levels besides the one that can be generated with the 15-level topology are ${V}_{\mathrm{Y}2},\left({{V}_{\mathrm{X}1}+ {V}_{\mathrm{Y}2}}\right),\left({V}_{\mathrm{X}2}\right.$ $\left.{+{V}_{\mathrm{Y}2}}\right),\left({{V}_{\mathrm{Y}1}+ {V}_{\mathrm{Y}2}}\right),\left({{V}_{\mathrm{X}1}+ {V}_{\mathrm{Y}1}+ {V}_{\mathrm{Y}2}}\right),\left({{V}_{\mathrm{X}1}+ {V}_{\mathrm{X}2}+ {V}_{\mathrm{Y}2}}\right),\left({V}_{\mathrm{X}2}\right.$ $\left.{+{V}_{\mathrm{Y}1}+ {V}_{\mathrm{Y}2}}\right)$, and $\left({{V}_{\mathrm{X}1}+ {V}_{\mathrm{X}2}+ {V}_{\mathrm{Y}1}+ {V}_{\mathrm{Y}2}}\right)$. Corresponding AC voltages are obtained at the output of HBI.

D. Switching and Voltage Stress Analysis of Proposed RSC- MLIs

In addition to presenting the switching table for the proposed topology, this study uniquely contributes by incorporating a detailed analysis of the voltage stress across each switch during different voltage levels. The voltage stress data, coupled with the switching table, can have significant implications for both power systems and industrial applications, especially in the manufacturing of inverters for different voltage ratings.

The precise assessment of voltage stress on individual switches is important for ensuring reliable MLI operation, particularly as it scales to higher voltage ratings. A comprehensive understanding of switch voltage stress aids in the design of more resilient and optimized systems. The voltage stress across the switch pair of HBI (S₁-S₁₁ and S₂-S₂₂) is not mentioned in the tables given in this section. Nevertheless, when a particular voltage level is applied and either switch pair (S₁-S₁₁ or S₂-S₂₂) is in the OFF state, the voltage stress on that pair equals the magnitude of that particular voltage level and the voltage stress on the other pair which is in on-state will be zero. Moreover, with the help of Tables I, II, and III, the total standing voltage of the inverter can be found, which is calculated as part of the comparative analysis given in Section IV. Based on the presented discussion, the mathematical expressions for the number of levels are given as

(1)

${N}_{\text{level }}= {2}^{\left(m + 1\right)} - 1 $

Similarly, for 7-level topology and 15/31 level topology, the number of switches, ${N}_{\text{switch }}$, can be given as per (2) and (3), respectively. In (2), four additional switches are needed for the H-Bridge inverter. Similarly, in (3), four additional switches and two bypass switches are needed.

(2)

${N}_{\text{switch }}= {2m}+ 4 $

(3)

${N}_{\text{switch }}= {2m}+ 6 $

The peak inverse voltage, ${PIV}$ is given as

(4)

${PIV}= \max \left\{{{V}_{\mathrm{{dc}}1},{V}_{\mathrm{{dc}}2},\ldots ,{V}_{\mathrm{{dc}}n}}\right\}$

E. Gating Scheme for the Proposed Modular RSC-MLI

Phase disposition sinusoidal PWM (PD-SPWM), reported in [28], is employed for the proposed modular RSC-MLI. The only difference is that instead of PWM pins of DSP, digital output pins are employed for providing the gating signal to the gate driver. TMS320F28335 DSP has twelve PWM pins and eighty-eight digital output pins. Due to the provision of complementary output, in actual there are only six independent PWM pins. The complementary PWM pins are very much suitable for the 2-level voltage source inverters however, they may not be very much beneficial in case of the MLI. In MLI, for a particular switch, another switch with complementary conduction period may not exist. Hence, individual PWM signals are required.

With limited PWM pins available in a DSP processor, multiple DSPs may be needed. This poses a challenge in terms of increased complexity, component count, need of synchronization and communication between multiple DSPs, etc. Rather by operating the DSP at clock frequency, the digital output pins can be utilized for gate pulse generation. Fig. 4 shows the block diagram representation of PD-SPWM modulation technique for the proposed 15-level modular RSC-MLI. Comparators, ${\mathrm{C}}_{1}$ to ${\mathrm{C}}_{7}$, individually compare the reference signal, ${V}_{\text{ref }}$, with level shifted carrier signals, ${\mathrm{{cr}}}_{1}- {\mathrm{{cr}}}_{7}$. The outputs of the seven comparators are subsequently fed to the mode selector. The mode selector generates switching pulses for each of the twelve switches employed in the proposed 15-level modular RSC-MLI. Mode selector generates individual gate pulses based on the switching table provided in Table II. Similarly, mode selector can be designed for generating individual gate pulses for the proposed 7-level and 31-level MLI based on Table I and Table III, respectively.

III. Loss Analysis

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The efficiency of MLI deteriorates mainly due to the conduction and switching losses occurring in the employed switches. The ON-state resistance of the IGBTs, ${R}_{\mathrm{{ON}}}$, antiparallel diode, ${R}_{\mathrm{{AD}}}$, and power diode, ${R}_{\mathrm{{PD}}}$, are mainly responsible for the conduction losses [29]. For determining conduction losses occurring in the proposed 7-level modular RSC-MLI, equivalent circuit is developed for each switching state as shown in Table IV. The conduction and switching losses for the proposed MLI are mathematically expressed by (5)-(13), where i indicates the instantaneous current flowing through the equivalent circuit, ${P}_{\mathrm{{Ci}}}$ and ${P}_{\mathrm{{Ca}}}$ indicate instantaneous and average conduction loss for the particular switching state, ${R}_{\mathrm{L}}$ is the load resistance, ${t}_{n}$ is the time period for which the n th switch state is active, and $T$ is the total time period for one cycle. The total conduction loss over one cycle, ${P}_{\mathrm{{CiT}}}$, can be computed as the summation of ${P}_{\mathrm{a}}$ over the entire cycle. ${P}_{\mathrm{{CiT}}}$ can be mathematically expressed as in (5), where $S$ is the switching state [29].

Switching losses, other major detrimental factor for efficiency, are caused due to the energy consumed in turning a switch ON or OFF. When the switch is in a state of partial conduction, neither completely turned ON nor OFF, leading to voltage and current overlap within the switch. This results in switching losses. For a switch, the average value of switching losses during the turn $\mathrm{{ON}}$ period, ${P}_{\mathrm{{swON}}}$, can be mathematically expressed as shown in (6),[17],(7),(8), and (9), where ${f}_{\mathrm{{sf}}}$ is switching frequency, ${t}_{\mathrm{{ON}}}$ is period of transition that starts at ${t}_{a}$ and ends at ${t}_{b},{v}_{\mathrm{{SwON}}}$ and ${i}_{\mathrm{{SwON}}}$ are the switch voltage and current during ${t}_{\mathrm{{ON}}},{V}_{\text{swOFF }}$ is the switch voltage before ${t}_{a},{I}_{\text{swON }}$ is the switch current after ${t}_{b}$, and ${V}^{\prime }$ is the voltage across the switch when it is in OFF state.

Similarly, the switching losses during the transition from turn ON to OFF,P_swOFF, can be mathematically expressed by (10)-(11), where ${t}_{\mathrm{{OFF}}}$ is period of transition that starts at ${t}_{a}^{\prime }$ and ends at ${t}_{b},{v}_{\text{SwOFF }}$ and ${i}_{\text{SwOFF }}$ are the switch voltage and current during ${t}_{\mathrm{{OFF}}},{V}_{\mathrm{{swON}}}$ is the switch voltage before ${t}_{a}^{\prime }$, and ${i}^{\prime \prime }$ is the switch current during ON state. The leakage current of the switch is neglected as it has significantly lower magnitude than ${I}_{\text{swON・}}$

(5)

${P}_{\mathrm{{CiT}}}= \mathop{\sum }\limits_{{S = 0}}^{4}{P}_{\mathrm{{Ca}}}\left(S\right)$

(6)

${P}_{\mathrm{{swON}}}= {f}_{\mathrm{{sf}}}{\int }_{{t}_{b}}^{{t}_{a}}{v}_{\mathrm{{SwON}}}\left(t\right){i}_{\mathrm{{SwON}}}\left(t\right)\mathrm{d}t $

(7)

$\begin{aligned}P_{\mathrm{swON}}= & f_{\mathrm{sf}}\left\{m_{i} t_{\mathrm{ON}}^{2}\left(V^{\prime}-2 m_{v} t_{a} / 2\right\}+\right. \\& f_{\mathrm{sf}}\left\{\left(m_{v} m_{i} t_{a}^{2}-V^{\prime} t_{a}\right) m_{i} t_{\mathrm{ON}}\right\}- \\& f_{\mathrm{sf}}\left\{\left(m_{v} m_{i} t_{\mathrm{ON}}^{3} / 3\right\}\right.\end{aligned}$

(8)

$m_{v}=V_{\mathrm{SWOFF}} / t_{\mathrm{ON}}$

(9)

$m_{i}=I_{\mathrm{swON}} / t_{\mathrm{ON}}$

(10)

$P_{\mathrm{SWOFF}}=f_{\mathrm{sf}} \int_{0}^{t_{0 F F}} v_{\mathrm{SWOFF}}(t) i_{\mathrm{SWOFF}}(t) \mathrm{d} t$

(11)

$\begin{aligned}P_{\mathrm{swOFF}}= & f_{\mathrm{sf}}\left\{m_{v}^{\prime} t_{\mathrm{OFF}}^{2}\left(i^{\prime \prime}-2 m_{i}^{\prime}\right) / 2\right\}+ \\& f_{\mathrm{sf}}\left\{\left(m_{i}^{\prime} t_{a}^{2}+i^{\prime \prime} t_{a}^{\prime}\right) m_{v}^{\prime} t_{\mathrm{OFF}}\right\}- \\& f_{\mathrm{sf}}\left\{\left(m_{v}^{\prime} m_{i}^{\prime} t_{\mathrm{OFF}}^{3} / 3\right\}\right.\end{aligned}$

(12)

$m_{v}^{\prime}=V_{\mathrm{SWOFF}} / t_{\mathrm{OFF}}$

(13)

$m_{i}^{\prime}=I_{\mathrm{swON}} / t_{\mathrm{OFF}}$

IV. Comparative Analysis

Less

Table V presents a comparison between the proposed topology and the earlier reported ones in terms of the number of levels, ${N}_{\mathrm{L}}$, number of switches, ${N}_{\mathrm{S}}$, number of gate-drivers, ${N}_{\mathrm{{GD}}}$, number of diodes, ${N}_{\mathrm{D}}$, number of capacitors, ${N}_{\mathrm{C}}$, number of DC sources, ${N}_{\mathrm{{DC}}}$, and total standing voltage per unit, TSV_PU. In this table, PT indicates the proposed topology. Additionally, the comparative analysis also includes whether the topology is modular or not. Moreover, in Table V, the topologies are clubbed together based on ${N}_{\mathrm{L}}$.

From the comparison presented, for generating 31-level [30]-[32] make use of two DC sources and four capacitors. Reference [30] uses a lesser number of switches than [31] and [32]. The proposed topology without the aid of any capacitor produces 31 levels. On the other hand, to obtain a 15-level output voltage,[33] makes use of the least number of switches but TSV_PU is very high. Reference [34] makes use of a higher number of switches but it’s TSV_PU is minimum. On the other hand, the topology reported in [35] requires one less switch as compared to the proposed topology for generating 15 levels. However, the topology from [35] needs four DC sources for the same voltage levels. Also, this topology is not modular. Topologies presented in [19],[36]-[38], produce 7-level output voltages. Out of these topologies, only the topologies presented in [19] and [38] are modular. However, they require a higher number of switches and three capacitors. References [36],[37] are having the same TSV_PU. However, the topology reported in [36] requires an additional four switches and three capacitors as compared to that reported in [37], which makes use of only two DC sources and eight switches. However, the TSV_PU for switches in the topology presented in [37] is higher than the proposed topology. The proposed topology necessitates fewer switches and avoids using any passive elements, which enhances compatibility and reduces the cost of the inverter.

Fig. 5 depicts four different MLI topologies, a, b, c, and d, presented in [39],[40],[41], and [42], respectively. These four topologies seem to be similar to the proposed topology. Topologies a, b, c, d, and the proposed topology are compared based on the average conduction time (ACT) of each switch during one output AC voltage. Higher ACT results in increased conduction losses and consequently increased heating of switches. This can cause thermal stress and reliability issues. ACT for proposed topology is 34.37%, 57.16%, and 84.17% for 7, 15, and 31 levels of output voltage, respectively. Topology a has a lesser value of ACT, however, TSV_PU is higher. TSV_PU increases as the number of modules increase with the number of levels. Also, as only symmetric configuration is possible in Topology a, adding one module (comprising of DC source and two switches) will result in a mere increment in the number of output voltage levels by two. Topologies b and c require the same number of components to produce the same number of voltage levels. However, due to the different placement of switches, ACT is different though TSV_PU is the same. Topology d has lesser TSV_PU and ACT but it makes use of a higher number of switches and DC sources. The proposed MLI topology may require more switches compared to Topologies $\mathrm{b}$ and $\mathrm{c}$, but it has a lesser value of TSV_PU.

TSV and switch count are important indices that directly or indirectly relate to the total cost of design and implementation. Usually, lower TSV indicates switches with lower voltage withstand capacity can be utilized and cost can be reduced and vice versa. Likewise, reducing the switch count for the same number of levels reduces total cost. However, in some cases, TSV will be higher, which increases the cost per switch. Topologies $\mathrm{b}$ and $\mathrm{c}$ have a lower switch count than the proposed MLI. However, their TSV is higher than the proposed topology. On the other hand, topology presented in D involves lower TSV than the proposed MLI but at the cost of increased switch count.

V. Experimental Results and Discussions

Less

For experimental validation, laboratory prototype model for the proposed 7-level, 15-level, and 31-level MLI topology was developed. Fig. 6 shows photograph of the developed experimental prototype. For the 7-level MLI, the two employed isolated DC power supplies are configured such that ${V}_{\mathrm{X}1}=$ ${40}\mathrm{\;V}$ and ${V}_{\mathrm{Y}1}= {30}\mathrm{\;V}$. Similarly, for 15- level MLI, the three isolated dc power supplies are required. They are configured such that ${V}_{\mathrm{X}1}= {35}\mathrm{\;V},{V}_{\mathrm{Y}1}= {25}\mathrm{\;V}$, and ${V}_{\mathrm{X}2}= {15}\mathrm{\;V}$. In case of 31-level MLI, four isolated DC power supplies are configured so that ${V}_{\mathrm{X}1}= {40}\mathrm{\;V},{V}_{\mathrm{Y}1}= {25}\mathrm{\;V},{V}_{\mathrm{X}2}= {20}\mathrm{\;V}$, and ${V}_{\mathrm{Y}2}= {10}\mathrm{\;V}$. The gate driver circuit is implemented using IC TLP250. To generate gate pulses, a level-shifted PWM technique is implemented with TMS320F28335 DSP. Digital storage oscilloscope Agilent-make DSO-X-2002A is employed for recording the waveforms. Power quality analyzer PHA5850 is used for THD measurement. Also, Load-I (comprising of series combination of ${165\Omega }$ resistor and ${20}\mathrm{{mH}}$ inductor) and Load-II (comprising of series combination of ${110\Omega }$ resistor and 20 $\mathrm{{mH}}$) are used in the study.

Fig. 7 illustrates the steady-state performance of the proposed 7-level, 15-level and 31-level modular RSC-MLI topology for Load-I and Load-II. In this case, the modulation index is 0.95 . The steady-state performance of 7-level modular RSC-MLI for Load-I and Load-II are shown in Fig. 7(a) and (b), respectively. For this 7-level topology, ${V}_{\mathrm{{Xl}}}= {40}\mathrm{\;V}$ and ${V}_{\mathrm{Y}1}=$ ${30}\mathrm{\;V}$. When supplying Load-I, the rms value of load voltage, ${v}_{1}$, is measured as ${45.39}\mathrm{\;V}$. Also, the rms value of load current, ${i}_{1}$, is recorded as 0.264 A.%THD for ${v}_{1}$ and ${i}_{1}$ are observed to be 6.5 and 5.0 . In this case, $\pm {28.58},\pm {36.20},\pm {66.68}$ and 0 V are observed to be the seven levels of ${v}_{1}$. When the load is increased from Load-I to Load-II, under the new steady-state, the rms value of ${i}_{1}$ increases from 0.264 A to 0.378A. Now, ${v}_{1}$ is observed to have a rms value of 43.96 V.

Fig. 7(c) and (d) show the steady-state performance of 15-level modular RSC-MLI for Load-I and Load-II, respectively. Similar to the earlier case, the modulation index is 0.95 . For 15-level modular RSC-MLI feeding Load-I, the rms values of ${v}_{1}$ and ${i}_{1}$ are measured as ${46.68}\mathrm{\;V}$ and ${0.278}\mathrm{\;A}$, respectively. The corresponding %THD is found to be 5.7 and 4.9. It is to be noted that in this case ${V}_{\mathrm{X}1}= {35}\mathrm{\;V},{V}_{\mathrm{Y}1}=$ ${25}\mathrm{\;V}$, and ${V}_{\mathrm{X}2}= {15}\mathrm{\;V}$. Now with the increase in load from Load-I to Load-II, the rms value of ${i}_{1}$ at the new steady-state is ${0.399}\mathrm{\;A}$. Consequently, the rms value of ${v}_{1}$ is reduced to ${45.48}\mathrm{\;V}$. In ${v}_{1},\pm {12.6},\pm {22.5},\pm {30.6},\pm {34.2},\pm {43.2},\pm {54.3},\pm {72}$ and $0\mathrm{\;V}$ are observed as the fifteen levels.

The steady-state performance of 31-level modular RSC-MLI for Load-I and Load-II are respectively demonstrated in Fig. 7(e) and (f). As for the other topologies, the modulation index is 0.95 . For 31-level modular RSC-MLI feeding Load-I, the measurements show ${v}_{1}$ and ${i}_{1}$ to have the rms values of ${60.92}\mathrm{\;V}$ and ${0.360}\mathrm{\;A}$, respectively. Correspondingly,%THD is measured to be 5.2 and 4.5 . As mentioned earlier, for this topology ${V}_{\mathrm{X}1}= {40}\mathrm{\;V},{V}_{\mathrm{Y}1}= {25}\mathrm{\;V},{V}_{\mathrm{X}2}= {20}\mathrm{\;V},{V}_{\mathrm{Y}2}= {10}\mathrm{\;V}$. The rise in load from Load-I to Load-II leads to an increased steady-state rms value of ${i}_{1}$. Compared to the rms value of 0.36 A, now the rms value of ${i}_{1}$ is observed as ${0.514}\mathrm{\;A}$. The rms value of ${v}_{1}$ is measured as 58.79 V. The dynamic performance of the proposed topology has been evaluated to verify its ability to function under sudden changes in loading conditions. The dynamic performance of the proposed 7-level, 15-level and 31-level modular RSC-MLI is analyzed under the change in load from Load-I to Load-II.

Figs. 8 to 10 illustrates ${v}_{1}$ and ${i}_{1}$ for 7-level,15-level and 31-level modular RSC-MLI during change in load from Load-I to Load-II. For all the three topologies, the increase in load from Load-I to Load-II results in increase in ${i}_{\mathrm{l}}$. However, with the increase in ${i}_{1}$, the on-state voltage drop across the switches increases, which results in minor reduction in ${v}_{1}$. This can be observed in case of all the three proposed MLI topologies. Thus, any increment in ${i}_{1}$ would results in increased on-state voltage drop across the switches and consequent reduction in rms value of ${v}_{1}$. The reverse is also true. Further, Figs. 8-10, confirm the satisfactory operation of the proposed topologies during the load change, with no abnormal behavior observed.

VI. Conclusion

Less

In this paper, a modular RSC-MLI for 7-level, 15-Level, and 31-level output voltage is proposed. A discussion on modules developed, the power structure of the proposed MLI topologies, the theory of operation, and the primary approach for modulation are presented. The formulation of switch losses is also presented. Phase disposition level-shifted PWM technique is utilized for gate pulse generation. Limited PWM pins are available in a DSP, which may not suffice for an MLI. To overcome this, the gating signals are generated at the digital output pins, which are in substantially higher numbers, are used instead of the PWM pins. Thereby, the need to use multiple DSPs and associated complexity is avoided. The modular construction of the proposed topology easily allows for increasing the levels by adding modules. The merits of the proposed topology are highlighted through a comparative analysis. From the comparative analysis, inference can be drawn that the proposed modular RSC-MLI topologies can provide staircase voltage with higher power quality while simultaneously decreasing the number of components, the total cost, and higher compatibility as no passive elements are involved. Finally, the proposed 7-level, 15-Level, and 31-level modular RSC-MLI topologies are assessed experimentally under steady-state and dynamic load change to validate the presented theory.

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Year 2024 volume 9 Issue 4

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doi: 10.24295/CPSSTPEA.2024.00018

Receive Date：2024-01-13
Online Date：2025-07-05
Published：2024-12-10

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Received：2024-01-13
Revised：2024-07-11
Accepted：2024-08-18

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Pandit Deendayal Energy University Department of Electrical Engineering, School of Energy Technology Gandhinagar India

Corresponding:

Amit V. Sant.

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表12种不同金属材料的力学参数

科 Family	属数 Number of genus	种数 Number of species	占总种数比例 Percentage of total species (%)	属 Genus	种数 Number of species	占总种数比例 Percentage of total species (%)
鹅膏菌科Amanitaceae	2	11	5.26	鹅膏菌属 Amanita	10	4.78
小菇科 Mycenaceae	2	12	5.74	丝盖伞属 Inocybe	5	2.39
多孔菌科 Polyporaceae	8	14	6.70	蜡蘑属 Laccaria	5	2.39
红菇科 Russulaceae	3	23	11.00	小皮伞属 Marasmius	6	2.87
				小菇属 Mycena	11	5.26
				光柄菇属 Pluteus	5	2.39
				红菇属 Russula	17	8.13
				栓菌属 Trametes	5	2.39

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TABLE I Switching Table for the Proposed 7-Level Modular RSC-MLI

STATE/ MODE	Module								V_JK
	X₁		Y₁		X₁		Y₁
	S_UX1	S_LX1	S_UY1	S_LY1	S_SUX1	S_LUX1	S_SUY1	S_LUY1
1	-	-	-	-	-	-	-	-	0
2	-	-	-	1	0	0	${V}_{\mathrm{a}}$	0	${V}_{\mathrm{Y}1}$
3	1	1	-	-	0	0	${V}_{\mathrm{a}}$	0	${V}_{\mathrm{X}1}$
4	1	-	1	-	0	0	0	0	${V}_{\mathrm{{Xl}}} + {V}_{\mathrm{{Yl}}}$

TABLE II Switching Table for the Proposed 15-Level Modular RSC-MLI

STATE/ MODE	Module						S_U	S_L	Voltage Across Switches
	X₁		Y₁		X₂				S_UX1	S_LX1	S_UY1	S_LY1	S_UX1	S_LX2	S_U	S_L
	S_UX1	S_LX1	S_UY1	S_LY1	S_UX1	S_LX2			V_SUX1	V_SLX1	V_SUY1	V_SLY1	V_SUX2	V_SLX2	V_SU	V_SL
1	-	-	-	1	-	1	-	1	${V}_{\mathrm{a}}$	0	${V}_{\mathrm{a}}$	0	${V}_{\mathrm{b}}$	0	0	0	${V}_{\mathrm{Y}1}$
2	1	1	-	-	-	1	-	1	0	0	${V}_{\mathrm{a}}$	0	${V}_{\mathrm{b}}$	0	0	0	${V}_{\mathrm{X}1}$
3	1	-	1	-	-	1	-	1	0	0	0	0	${V}_{\mathrm{b}}$	0	0	0	${V}_{\mathrm{{Xl}}} + {V}_{\mathrm{{Yl}}}$
4	-	-	-	-	1	1	1	-	${V}_{\mathrm{e}}$	$- {V}_{\mathrm{g}}$	${V}_{\mathrm{f}}$	${V}_{\mathrm{a}}$	0	0	0	0	${V}_{\mathrm{X}2}$
5	-	-	-	1	1	1	-	-	${V}_{\mathrm{a}}$	0	${V}_{\mathrm{a}}$	0	0	0	0	0	${V}_{\mathrm{X}1} + {V}_{\mathrm{X}2}$
6	1	1	-	-	1	1	-	-	0	0	${V}_{\mathrm{a}}$	0	0	0	0	0	${V}_{\mathrm{X}1} + {V}_{\mathrm{X}2}$
7	1	-	1	-	1	1	-	-	0	0	0	0	0	0	0	0	${V}_{\mathrm{X}1} + {V}_{\mathrm{X}2} + {V}_{\mathrm{Y}1}$

note: ${V}_{\mathrm{a}}= {V}_{\mathrm{Y}1};{V}_{\mathrm{b}}= {V}_{\mathrm{X}2};{V}_{\mathrm{e}}= \frac{5}{6}{V}_{\mathrm{X}1};{V}_{\mathrm{f}}= \frac{4}{3}{V}_{\mathrm{Y}1};{V}_{\mathrm{g}}= \frac{{V}_{\mathrm{Y}1}}{3}$

TABLE III Switching Table for the Proposed 31-Level Modular RSC-MLI

STATE/ MODE	Module								S_3Y2	S_U	Voltage Across Switches
	X₁		Y₁		X₂		Y₂				S_UX1	S_LX1	S_UY1	S_LY1	S_UX2	S_LX2	S_LY2	S_3Y2	S₁₆
	S_UX1	S_LX1	S_UY1	S_LY1	S_UX2	S_LX2	S_LY2	S_UY2			V_SUX1	V_SLX1	V_SUY1	V_SLY1	V_SUX2	V_SLX2	V_SUY2	V_SLY2	V_S3Y2	V_SU
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0
2	-	-	-	1	-	1	D	1	-	-	${V}_{\mathrm{a}}$	0	${V}_{\mathrm{a}}$	0	${V}_{\mathrm{d}}$	0	0	0	${V}_{\mathrm{b}}$	0	${V}_{\mathrm{Y}1}$
3	1	1	-	-	-	1	D	1	-	-	0	0	${V}_{\mathrm{a}}$	0	${V}_{\mathrm{d}}$	0	0	0	${V}_{\mathrm{b}}$	0	${V}_{\mathrm{X}1}$
4	1	-	1	-	-	1	D	1	-	-	0	0	0	0	${V}_{\mathrm{d}}$	0	0	0	${V}_{\mathrm{b}}$	0	${V}_{3}$
5	-	-	-	-	-	-	-	1	1	1	${V}_{\mathrm{e}}$	${V}_{\mathrm{g}}$	${V}_{\mathrm{f}}$	${V}_{\mathrm{a}}$	${V}_{\mathrm{b}}$	0	${V}_{\mathrm{b}}$	0	0	0	${V}_{\mathrm{Y}2}$
6	-	-	-	1	-	-	-	1	1	-	${V}_{\mathrm{e}}$	0	${V}_{\mathrm{a}}$	0	${V}_{\mathrm{b}}$	0	${V}_{\mathrm{b}}$	0	0	0	${V}_{5}$
7	1	1	-	-	-	-	-	1	1	-	0	0	${V}_{\mathrm{a}}$	0	${V}_{\mathrm{b}}$	0	${V}_{\mathrm{b}}$	0	0	0	${V}_{6}$
8	1	-	1	-	-	-	-	1	1	-	0	0	0	0	${V}_{\mathrm{b}}$	0	${V}_{\mathrm{b}}$	0	0	0	${V}_{7}$
9	-	-	-	-	1	1	-	-	-	1	${V}_{\mathrm{e}}$	${V}_{\mathrm{g}}$	${V}_{\mathrm{f}}$	${V}_{\mathrm{a}}$	0	0	${V}_{\mathrm{b}}$	0	0	0	${V}_{\mathrm{X}2}$
10	-	-	-	1	1	1	-	-	-	-	${V}_{\mathrm{a}}$	0	${V}_{\mathrm{a}}$	0	${V}_{\mathrm{b}}$	0	0	0	0	0	${V}_{9}$
11	1	1	-	-	1	1	0	-	-	-	0	0	${V}_{\mathrm{a}}$	0	0	0	${V}_{\mathrm{b}}$	0	0	0	${V}_{10}$
12	1	-	1	-	1	1	-	-	-	-	0	0	0	0	0	0	${V}_{\mathrm{b}}$	0	0	0	${V}_{11}$
13	-	-	-	-	1	-	-	1	1	1	${V}_{\mathrm{e}}$	${V}_{\mathrm{g}}$	${V}_{\mathrm{f}}$	${V}_{\mathrm{a}}$	0	0	0	0	0	0	${V}_{12}$
14	-	-	-	1	1	-	1	-	1	-	${V}_{\mathrm{a}}$	0	${V}_{\mathrm{a}}$	0	0	0	0	0	0	0	${V}_{13}$
15	1	1	0	0	1	-	1	-	1	-	0	0	${V}_{\mathrm{a}}$	0	0	0	0	0	0	0	${V}_{14}$
16	1	-	1	-	1	-	1	-	1	-	0	0	0	0	0	0	0	0	0	0	${V}_{15}$

note:$V_{3}=V_{\mathrm{X} 1}+V_{\mathrm{Y} 1} ; V_{5}=V_{\mathrm{Y} 1}+V_{\mathrm{Y} 2} ; V_{6}=V_{\mathrm{X} 1}+V_{\mathrm{Y} 2} $;$V_{7}=V_{\mathrm{X} 1}+V_{\mathrm{Y} 2}+V_{\mathrm{Y} 1} ; V_{9}=V_{\mathrm{X} 2}+V_{\mathrm{Y} 1} ; V_{10}=V_{\mathrm{X} 2}+V_{\mathrm{X} 1}$$V_{11}=V_{\mathrm{X} 2}+V_{\mathrm{X} 1}+V_{\mathrm{Y} 1} ; V_{12}=V_{\mathrm{X} 2}+V_{\mathrm{Y} 2} $;$V_{13}=V_{\mathrm{X} 2}+V_{\mathrm{Y} 2}+V_{\mathrm{Y} 1} ; V_{14}=V_{\mathrm{X} 2}+V_{\mathrm{Y} 2}+V_{\mathrm{X} 1} $;$V_{15}=V_{\mathrm{X} 2}+V_{\mathrm{Y} 2}+V_{\mathrm{X} 1}+V_{\mathrm{Y} 1}$$V_{\mathrm{a}}=V_{\mathrm{Y} 1} ; V_{\mathrm{b}}=V_{\mathrm{Y} 2} $;$V_{\mathrm{d}}=V_{\mathrm{X} 2} ; V_{\mathrm{e}}=\frac{5}{6} V_{\mathrm{X} 1} $;$V_{\mathrm{f}}=\frac{4}{3} V_{\mathrm{Y} 1} ; V_{\mathrm{g}}=\frac{V_{\mathrm{Y} 1}}{3}$

TABLE IV Equivalent Circuits of the Proposed 7-Level Modular RSC-MLI

Equivalent Circuit	/Instantaneous Current/ Instantaneous Conduction Loss
	$\pm {V}_{\mathrm{X}1}$ $\frac{{V}_{\mathrm{X}1} - {V}_{d}}{4{R}_{\mathrm{{ON}}} + {R}_{\mathrm{{PD}}} + {R}_{\mathrm{L}}}$ ${i}_{\mathrm{{sw}}}{}^{2}\left({4{R}_{\mathrm{{ON}}} + {R}_{\mathrm{{PD}}}}\right)$
	$\pm {V}_{\mathrm{Y}1}$ $\frac{{V}_{\mathrm{Y}1} - {V}_{d}}{3{R}_{\mathrm{{ON}}} + {R}_{\mathrm{{PD}}} + {R}_{\mathrm{L}}}$ ${i}_{\mathrm{{sw}}}{}^{2}\left({3{R}_{\mathrm{{ON}}} + {R}_{\mathrm{{PD}}}}\right)$
	$\pm \left({{V}_{\mathrm{X}1} + {V}_{\mathrm{Y}1}}\right)$ $\frac{{V}_{\mathrm{X}1} + {V}_{\mathrm{Y}1} - {V}_{d}}{4{R}_{\mathrm{{ON}}} + {R}_{\mathrm{L}}}$ ${i}_{\mathrm{{sw}}}{}^{2}\left({4{R}_{\mathrm{{ON}}}}\right)$

TABLE V Comparison of the Proposed Modular RSC-MLI With Earlier Reported TOPOLOGIES

PT	N_L	N_S	N_GD	N_D	N_C	N_DC	Modular	TSV_PU
[30]	31	14	14	2	4	2	Yes	6.0
[31]	31	18	18	2	4	2	Yes	5.6
[32]	31	16	16	2	4	2	Yes	5.6
PT	31	14	14	4	0	4	Yes	5.8
[33]	15	8	8	8	0	4	Yes	7
[34]	15	16	16	0	0	3	Yes	1.9
[35]	15	12	11	0	0	4	No	5.1
PT	15	12	12	3	0	3	Yes	4.7
[36]	7	12	11	0	2	1	No	5.3
[37]	7	8	8	0	0	2	No	5.3
[19]	7	11	11	3	3	1	yes	5.0
[38]	7	13	13	4	3	1	yes	5.7
PT	7	8	8	2	0	2	Yes	4.6

Fig. 1. Power circuit configuration of (a) proposed modular RSC-MLI, and (b) module $\mathrm{X}$ and $\mathrm{Y}$ .

Fig. 2. SDVG configuration for the proposed (a) 7-level modular RSC-MLI, and (b) 15-level modular RSC-MLI.

Fig. 3. Power circuit configuration of SDVG for the proposed 31-level modular RSC-MLI.

Fig. 4. PD-SPWM modulation technique for the proposed 15-level modular RSC-MLI.

Fig. 5. Four different MLI topologies similar to the proposed topology.

Fig. 6. Hardware set-up for the proposed modular RSC-MLI.

Fig. 7. Performance of (a) 7-level MLI with Load-I,(b) 7-level MLI with Load-II,(c) 15-level MLI with Load-I,(d) 15-level MLI with Load-II,(e) 31-level MLI with Load-I, and (f) 31-level MLI with Load-II under steady-state.

Fig. 8. Performance of 7-level MLI during change in load from Load-I to Load-II.

Fig. 9. Performance of 15-level MLI during change in load from Load-I to Load-II.

Fig. 10. Performance of 31-level MLI during the change in load from Load-I to Load-II.

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