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A Generalized Partial Fault-Tolerant Single-Phase Common-Ground Multilevel Inverter for PV System
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Soniya AGRAWAL1, 2, Manoranjan SAHOO3, Sateesh Kumar KUNCHAM4, Yam Prasad SIWAKOTI5
CPSS Transactions on Power Electronics and Applications | 2025, 10(1) : 10 - 21
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CPSS Transactions on Power Electronics and Applications | 2025, 10(1): 10-21
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A Generalized Partial Fault-Tolerant Single-Phase Common-Ground Multilevel Inverter for PV System
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Soniya AGRAWAL1, 2, Manoranjan SAHOO3, Sateesh Kumar KUNCHAM4, Yam Prasad SIWAKOTI5
Affiliations
  • 1 National Institute of Technology Tiruchirappalli Tiruchirappalli 620015 India
  • 2 B.M.S. College of Engineering Bangalore 560019 India
  • 3 National Institute of Technology Rourkela Rourkela 769008 India
  • 4 National Institute of Technology Tiruchirappalli Electrical Engineering Department Tiruchirappalli 620015 India
  • 5 University of Technology Sydney Sydney 2007 Australia

    • Soniya Agrawal has received her B.E. degree in electrical engineering from Govt. Engineering College Raipur, C.G. and M.Tech degrees in power electronics from BMSCE Bangalore, Karnataka, India. She is an Assistant Professor with BMS College of Engineering Bangalore, since 2013. Currently she is working towards her Ph.D. degree in National Institute of Technology Tiruchirappalli, Tamil Nadu, India. Her research interests include multilevel inverters and fault tolerance for power converters for PV and EV applications.

    Manoranjan Sahoo received the M.Tech. and Ph.D. degrees in power electronics and power systems from the Indian Institute of Technology Hyderabad, India, in 2015 and 2017, respectively. He is currently an Assistant Professor with the Department of Electrical Engineering, National Institute of Technology Rourkela, India. His research interests include single-stage buck-boost inverters, fault-tolerant multilevel inverters, and electrical drives for EV applications.

    Sateesh Kumar Kuncham received the B.Tech and M.Tech degrees from Jawaharlal Nehru Technological University Kakinada, India, in 2012 and 2014, respectively, and the Ph.D. degree from the National Institute of Technology Warangal, India, in 2021. He was the recipient of Institute Post-Doctoral Fellowship with IIT Delhi from May 2022 to October 2022. He is currently an Assistant Professor with the Department of Electrical and Electronics Engineering, National Institute of Technology Tiruchirappalli, Tamil Nadu, India. His research interests include for PV power generation system, DC-DC converter topologies for EV charging, multilevel inverter, leakage current and common mode noise elimination.

    Yam Prasad Siwakoti received the B.Tech. degree in electrical engineering from the National Institute of Technology, Hamirpur, India, in 2005, the master's degree in electrical power engineering from the Norwegian University of Science and Technology, Trondheim, Norway, and Kathmandu University, Dhulikhel, Nepal, in 2010, and the Ph.D. degree in electronic engineering from Macquarie University, Sydney, Australia, in 2014. He was a Postdoctoral Fellow with the Department of Energy Technology, Aalborg University, Denmark, in 2014-2016. He was a Visiting Professor at the Department of Engineering Science, University of Oxford, Oxford, UK, in 2023. He was also a Visiting Scientist with the Fraunhofer Institute for Solar Energy Systems, Freiburg, Germany, in 2018-2023. His research has been recognized by a series of awards and recognition including the most prestigious Friedrich Wilhelm Bessel Research Award from the Alexander von Humboldt Foundation, Germany, in 2022, and the Green Talent Award from the Federal Ministry of Education and Research, Germany, in 2016. Dr. Siwakoti is currently an Associate Professor at the University of Technology Sydney.

Published: 2025-03-10 doi: 10.24295/CPSSTPEA.2025.00002
Outline
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The common ground multilevel inverter (MLI) is highly appreciated in transformerless photovoltaic (PV) systems, which have improved leakage current performance and reduced filter size. The faulttolerant (FT) capability is essential in a common ground inverter to enhance the reliability of the system. This paper highlights a FT strategy for singlephase common ground MLI under different open switch fault conditions. The proposed circuit can selfbalance the voltage across the switched capacitor (SC) in normal and switch open circuit (OC) fault conditions. Moreover, the employed modulation scheme enables the SCs to be connected in series or parallel to obtain a wide range of output voltages with reduced input voltage. Further, the circuit can be extended for higher voltage levels by adding SC cells. A detailed Markov reliability and cost function assessment highlights the merits of the proposed inverter over counter topologies. Finally, the inverter's operational feasibility and effectiveness are validated through 500 W prototype experimentally.

Common ground  /  fault-tolerant  /  multilevel inverter  /  reliability  /  switched capacitor
Soniya AGRAWAL, Manoranjan SAHOO, Sateesh Kumar KUNCHAM, Yam Prasad SIWAKOTI. A Generalized Partial Fault-Tolerant Single-Phase Common-Ground Multilevel Inverter for PV System[J]. CPSS Transactions on Power Electronics and Applications, 2025 , 10 (1) : 10 -21 . DOI: 10.24295/CPSSTPEA.2025.00002
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I. INTRODUCTION
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THE global move toward clean and sustainable energy is evident by widespread adoption of photovoltaic (PV) systems in industries, homes, and power generation stations. Inverters play a crucial role in PV-based power conversion systems. Transformerless inverters (TLIs) are compact, low-cost solutions for grid-connected PV systems [1]. However, removing transformers from inverters introduces leakage current issues due to the PV panel’s parasitic capacitance. The traditional transformerless three-level (3L) H-bridge inverter with boost converter has less component count, but it is able to supply a 3L output which in turn requires higher size of filter to obtain a sinusoidal waveform. Consequently, boost with seven-level (7L) H-bridge inverter was presented in the literature [2] to increase the output voltage levels. But it comes with an increased number of switches, DC sources, gate driver circuitry, and passive components. Further, the conventional H-bridge based inverters are suffering from the issue of leakage current due to PV parasitic capacitance. This results in electromagnetic compatibility (EMC) problems, low power quality, and shorter system lifespan. Thus, the above-said topologies cannot be used directly for the PV applications as per the German VDE 0126- 1-1 standard (i.e., common mode leakage current should be less than ${100}\mathrm{\;{mA}}$）. Also, the use of front-end boost converters is more susceptible to instability especially at higher duty ratios, and involve complex inductor design.
To address the above said issues literature proposes that minimizing leakage current in TLIs by forming a common ground connection between the load-neutral and PV-negative terminals is the most effective solution [3]-[5]. As there is a chance of the failure of a switch in a solar-powered inverter due to sudden load changes, overheating, or manufacturing defects, it results in the shutdown of the entire system. However, the continuity of supply is essential for critical off-grid solar applications like lighting in remote areas, water pumping, power supply for security surveillance, and medical emergency systems. Therefore, a FT system is an important aspect in the above applications to retain the continuous supply of electric power. For instance, an off-grid solar-based water pumping system in remote areas is driven by an inverter [6]. If a switch fault occurs in the inverter, the water pumping will stop, disrupting essential day-to-day activities. With a FT inverter, the system would continue to supply water even in the event of a switch failure, ensuring uninterrupted operation. Therefore, recent research has emphasized the development of multilevel inverters (MLIs) with integrated FT capabilities. Based on the availability of voltage at the load during post-fault period, the inverter can be named as partial FT or complete FT topology. A complete FT hybrid cascaded H-bridge (CHB) MLI [7] is presented, utilizing cross-coupled CHB for fault tolerance. However, this topology has a higher switch count and demands a greater number of independent DC sources. To address this, [8] proposes a FT 7L CHB inverter with fewer switches. In several cases, complete FT operation is not practically possible due to the requirement of uneven voltage sources and the nonavailability of redundant paths.
To address that, in [9], a 7L inverter was adapted for partial fault tolerance with a greater number of DC sources. The inverter in [10],[11] employs three DC sources and a high switch count. Also, using an H-bridge at the output stage for polarity generation results in high total standing voltage (TSV). In [12], a resilient FT five-level (5L) inverter is discussed. While the topology has fewer switching devices, the use of clamping diodes increases conduction losses in the system. The topology in [13] offers fault tolerance with fewer switches for 5L output voltage under most faults but is limited to buck mode operation. In [14],[15], FT 5L inverters for single and multiple-switch faults are described. Madhukar Rao A., et al. introduce a partial FT inverter using a tap-changing transformer to preserve power rating, raising system costs [16].
Moreover, the explored FT inverter topologies face challenges in direct application to PV systems due to parasitic capacitance-induced leakage current. Thus, they cannot be used directly for the PV applications. To address this, additional common-mode filters or transformers are needed, increasing system size, cost, complexity, and power losses. CG-based inverters can mitigate leakage current, but achieving both FT and multilevel operation is challenging due to the limited number of redundant states. A FT operation in MLI with a CG is an important aspect of a PV system, however, it has not been adequately explored in the literature. Therefore, the authors are driven to explore the development of a novel CG based FT MLI with inherent voltage boosting for standalone PV applications. Further, the key attributes of the suggested inverter are as follows:
• Manages single or multiple switch faults with the least or no modification in pulse width modulation (PWM) scheme.
• Eliminating the leakage current with a single source and handling faults while giving generalized multilevel output voltages.
• Three-time inherent voltage boosting.
• Self-balanced voltage across switched capacitors (SCs) (${C}_{1}$ and ${C}_{2}$) pre- and post-fault operation.
• Markov reliability, component comparison, and cost function (CF) analysis indicate the proposed topology’s suitability for standalone PV systems.
The rest of the paper is organized as follows: Section II covers the topology description and operation of the proposed inverter, modulation and fault tolerance scheme. Section III analyzes inverter’s reliability. Section IV deals with simulation and hardware validation. Section V details the voltage current and loss analysis of the proposed inverter. Section VI gives the maximum power point tracking (MPPT) approach for the proposed inverter. Section VII compares the presented topology with its counterparts. Finally, Section VIII concludes the paper.
II. Proposed Generalized Common Ground Fault- TOLERANT MLI
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A. Topology Description and Mode of Operation
The schematic of the generalized structure for the proposed common ground FT multilevel inverter (CGFTMLI) is illustrated in Fig. 1. The blue-coloured line shows the redundant switches added for fault tolerance. The black-coloured line shows the inverter during normal operation. The N number of basic SC cells can be cascaded (as shown in multi-colour cells) to generate the 2n+3 output voltage levels, which requires an n+1 number of switched capacitors and a 3n+5 number of switches. Each basic cell can generate a $5\mathrm{\;L}$ output voltage, and it can be generalized to 2n+3 output voltage levels.
The 7L inverter is considered for the FT operation analysis with n=2,SC cells, as shown in Fig. 2(a). It consists of 11 controlled switches (T1-T11), one input DC link capacitor Cin, and three (C1,C2,C3). The series and parallel configuration of the SC generates 7L voltage with three times input voltage boosting. The main inverter switching table for various switches in different modes of operation (V1-V7) during normal operation is given in Table I. It outlines the inverter’s various switch conditions during operational modes. In mode ${\mathrm{M}}_{1},{V}_{\mathrm{{AN}}}$ is $+ 3{V}_{\mathrm{{dc}}}$ with ${C}_{1},{C}_{2}$, and ${C}_{3}$ discharging in series. In mode ${\mathrm{M}}_{2},{V}_{\mathrm{{AN}}}$ drops to $+ 2{V}_{\mathrm{{dc}}};{C}_{2}$ discharges in series and ${C}_{3}$ in parallel. Mode ${\mathrm{M}}_{3}$ realizes ${V}_{\mathrm{{AN}}}$ at $+ {V}_{\mathrm{{dc}}}$, with all capacitors charging in parallel, acting as an additional DC link. In mode ${\mathrm{M}}_{4},{V}_{\mathrm{{AN}}}$ is $0{V}_{\mathrm{{dc}}}$, allowing load current to freewheel through ${\mathrm{T}}_{10}$ and ${\mathrm{T}}_{11}$, with capacitors charging in parallel. Mode ${\mathrm{M}}_{5}$ drops ${V}_{\mathrm{{AN}}}$ to $- {V}_{\mathrm{{dc}}}$, discharging all capacitors in parallel. In mode ${\mathrm{M}}_{6}$, ${V}_{\mathrm{{AN}}}$ is $- 2{V}_{\mathrm{{dc}}}$, with ${C}_{1}$ and ${C}_{2}$ discharging in parallel and ${C}_{3}$ in series. Finally, mode ${\mathrm{M}}_{7}$ achieves $- 3{V}_{\mathrm{{dc}}}$, with all capacitors discharging in series [17].
The switch faults significantly impact the operation of the main inverter, leading to the unavailability of most voltage levels in the event of any switch fault. Four redundant switches (TR1-TR4) have been added to the circuit to tolerate the various switch faults. The FT analysis and corresponding modulation scheme are explained in the following subsections.
B. Fault Tolerant Analysis
The effect of open circuit (OC) switch faults of the proposed inverter has been analyzed in detail for the single switch fault, double and triple switch fault scenarios, and availability of various voltage levels during open fault conditions have been listed in Table II. Additionally, the fast-acting relays associated with each switch will activate in response to a short-circuit fault, converting it into an open-circuit fault [18], [19]. It has to be noted that there are 11 cases possible for single switch fault, $\mathrm{C}\left({{11},2}\right) = {11}!/\left({9! * 2!}\right) = {55}$, combination for double switch fault and $\mathrm{C}\left({{11},3}\right) = {11}!/\left({8! * 3!}\right) = {165}$ combination for triple switch fault is possible. In Table II, all single-switch fault cases and potential double- and triple-switch fault cases have also been listed, and some of the possible faults and reductant states are illustrated in Fig. 2.

  1. Single switch fault: In case of a fault on the switch T3 during the mode ${\mathrm{M}}_{1}$, the $3{V}_{\mathrm{{dc}}}$ voltage level can be generated by activating redundant switch ${\mathrm{T}}_{\mathrm{{R1}}}$ as shown in Fig. 2 (b). If the switch fault occurs in switch ${\mathrm{T}}_{6}$ in mode ${\mathrm{M}}_{2},2{V}_{\mathrm{{dc}}}$ voltage level can be obtained without any modification in PWM scheme as given in Fig. 2 (c).

  2. Double switch fault: When fault occurs in switch ${\mathrm{T}}_{6}$ and ${\mathrm{T}}_{9}$ simultaneously in mode ${\mathrm{M}}_{3}$, in this case the capacitor ${C}_{1}$ continues to provide ${V}_{\mathrm{{dc}}}$ voltage level at the output as in Fig. 2 (d). Also, during mode ${\mathrm{M}}_{4}$, if fault occur on ${\mathrm{T}}_{10}$ and ${\mathrm{T}}_{11}$ as in Fig. 2 (e), the redundant switches ${\mathrm{T}}_{\mathrm{R}3}$ and ${\mathrm{T}}_{\mathrm{R}4}$ can be switched ” $\mathrm{{ON}}$ “. Mode ${\mathrm{M}}_{5},{\mathrm{\;T}}_{2},{\mathrm{\;T}}_{5}$ fault can be replaced by redundant switches ${\mathrm{T}}_{\mathrm{R}2}$ and ${\mathrm{T}}_{\mathrm{R}3}$ in Fig. 2(f).

  3. Triple switch fault: In the event of simultaneous three switches i.e, ${\mathrm{T}}_{2},{\mathrm{\;T}}_{5}$ and ${\mathrm{T}}_{10}$ failure in mode ${\mathrm{M}}_{6}$ as Fig. 2(g) and similarly in case of ${\mathrm{T}}_{2}$ and redundant switches to get ${\mathrm{T}}_{2},{\mathrm{\;T}}_{4}$ and ${\mathrm{T}}_{11}$ failure in mode ${\mathrm{M}}_{7}$ as Fig. 2(h), with redundant switches and alternate path for the $- 2{V}_{\mathrm{{dc}}}$ and $- 3{V}_{\mathrm{{dc}}}$ voltage levels can be obtained. Table II outlines the accessibility of switching states and voltage levels within the proposed topology under various other fault conditions, incorporating redundant switches. Therefore, the suggested CGFTMLI can tolerate failure of single and multiple switches while providing a continuous supply to the load.

C. Fault Tolerant Modulation Scheme
The modulation scheme for the proposed FT inverter is determined by the number of output voltage levels obtained during post-fault. The level-shifted pulse width modulation (LS-PWM) scheme has been adopted for 7L voltage generation. The availability of voltage levels during OC fault and fault tolerant strategy has been shown in Table II. It shows that a 7L output voltage can be obtained if any single, double, or triple fault occurs on switches ${\mathrm{T}}_{2},{\mathrm{\;T}}_{3},{\mathrm{\;T}}_{10}$, and ${\mathrm{T}}_{11}$ during post-fault operation. In this case, the reference voltage ${V}_{\text{ref }}$ has been taken with an amplitude ${A}_{\mathrm{c}} = {A}_{\text{ref }}/3$, as shown in Fig. 3(a). Similarly, for faults on the switches ${\mathrm{T}}_{4},{\mathrm{\;T}}_{5},{\mathrm{\;T}}_{6},{\mathrm{\;T}}_{7}$ or ${\mathrm{T}}_{8}$ $5\mathrm{\;L}$ output voltage is obtained with ${V}_{\text{ref }}$ amplitude ${A}_{\mathrm{c}} = {A}_{\text{ref }}/2$ as given in Fig. 3(b). In case of a fault on any two series switches (for example, switch ${\mathrm{T}}_{4}$ and ${\mathrm{T}}_{6}$ simultaneously) a $3\mathrm{\;L}$ output voltage can be achieved with ${V}_{\text{ref }}$, having, ${A}_{\mathrm{c}} = {A}_{\text{ref }}$ shown in Fig. 3(c). The flowchart in Fig. 4 illustrates the procedural steps for implementing the LS-PWM scheme in normal and fault conditions.
D. Self-Voltage Balancing Analysis of the SCs
Table I reveals that all three SCs are charged with the same voltage for an equal amount of time and are discharged simultaneously. Therefore, the proposed inverter has achieved self-voltage balancing of the SC [20]. The voltage across each capacitor is naturally balanced to ${V}_{\mathrm{{dc}}}$ by the principle of charge-second balance of the capacitor in a fundamental cycle of the output voltage. As per Table I, the capacitors are charged during modes ${\mathrm{M}}_{3}$ and ${\mathrm{M}}_{4}$, and the capacitors are discharged in all the other modes of operation. Also, in the mode ${\mathrm{M}}_{4}$, the load current freewheels. Considering half-wave symmetry to the output voltage (Vac) and current (iac) with the load across the inverter as ${Z}_{\mathrm{L}}$, the average current through capacitors during each mode of operation is given by
$ \left\langle {i}_{\mathrm{c}}^{\mathrm{{M1}}}\right\rangle = 3{v}_{\mathrm{c}}/{Z}_{\mathrm{L}},\left\langle {i}_{\mathrm{c}}^{\mathrm{{M2}}}\right\rangle = 2{v}_{\mathrm{c}}/{Z}_{\mathrm{L}},\left\langle {i}_{\mathrm{c}}^{\mathrm{{M3}}}\right\rangle = {V}_{\mathrm{{dc}}}/{Z}_{\mathrm{L}},\left\langle {i}_{\mathrm{c}}^{\mathrm{{M4}}}\right\rangle = 0, $
$ \left\langle {i}_{\mathrm{c}}^{\mathrm{{M5}}}\right\rangle = 3{v}_{\mathrm{c}}/{Z}_{\mathrm{L}},\left\langle {i}_{\mathrm{c}}^{\mathrm{{M6}}}\right\rangle = 2{v}_{\mathrm{c}}/{Z}_{\mathrm{L}},\left\langle {i}_{\mathrm{c}}^{\mathrm{{M7}}}\right\rangle = {v}_{\mathrm{c}}/{Z}_{\mathrm{L}} $
Where ${v}_{\mathrm{c}}$ is the voltage across each capacitor. Using the above relations, the net charge(Q)delivered/absorbed by capacitors over the fundamental cycle (with time period $T$) is given by
$ Q = \left\{ {\left\langle {i}_{\mathrm{c}}^{\mathrm{{M1}}}\right\rangle + \left\langle {i}_{\mathrm{c}}^{\mathrm{{M2}}}\right\rangle + \left\langle {i}_{\mathrm{c}}^{\mathrm{{M3}}}\right\rangle + \left\langle {i}_{\mathrm{c}}^{\mathrm{{M4}}}\right\rangle - \left\langle {i}_{\mathrm{c}}^{\mathrm{{M5}}}\right\rangle - \left\langle {i}_{\mathrm{c}}^{\mathrm{{M6}}}\right\rangle - \left\langle {i}_{\mathrm{c}}^{\mathrm{{M7}}}\right\rangle }\right\} T $
$v =$ Available, $- =$ Not available
The average charge(Q)passing through an ideal capacitor must be zero for a periodic voltage in steady-state conditions. By substituting (1) with $Q = 0,\left(2\right)$ simplifies to
$ 0 = \left({{V}_{\mathrm{{dc}}} - {v}_{\mathrm{c}}}\right) /{Z}_{\mathrm{L}} $
This results in ${v}_{\mathrm{c}} = {V}_{\mathrm{{dc}}}$, which implies that the capacitor exhibits self-voltage balancing ability without requiring any voltage/current sensors.
III. RELIABILITY ANALYSIS
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Predicting reliability in power electronic converters is essential for manufacturers and users. If the converter unexpectedly fails, it can cause significant economic losses. Reliability assessment identifies potential failure modes, enabling careful maintenance and reducing the risk of sudden breakdowns. The process of reliability assessment for the proposed inverter is summarized in Fig. 5. The power semiconductor devices are the most fragile components of power electronic systems. The main factors causing the aging failure of power devices are thermal stresses which are caused by the means temperature [21]. Initially, thermal modeling of the inverter on the piecewise linear electrical simulation (PLECS) platform evaluates power loss by referencing the manufacturer’s data sheet for various components. The failure rates of switches and capacitors are determined using obtained power loss data [22]. Subsequently, the Markov chain reliability assessment derives the reliability function
$ R\left(t\right) = {e}^{-{\lambda t}} $
Where, $\lambda$ is the component’s failure rate in failures $/{10}^{6}\mathrm{\;h}$, which has been calculated as follows:
The failure rate of the components $\left({\lambda }_{\mathrm{z}}\right)$ is defined as
$ {\lambda }_{\mathrm{z}} = {\lambda }_{\text{zbase }}\mathop{\prod }\limits_{{x = 1}}^{n}{\alpha }_{\mathrm{x}} $
Where, ${\lambda }_{\text{base }}$ is the base failure rate of the component, N is the number of factor $\left(\alpha \right)$ affecting the failure rate of the components.
The various factors affecting the failure rate of the components are temperature factor $\left({\alpha T}\right)$, quality factor $\left({\alpha Q}\right)$, application factor $\left({\alpha A}\right)$, capacitance factor (acv), stress factor (aS), and environment factor (aE). Therefore, the failure rate for switch (SI) nd capacitor (Ci) can be calculated as below:
(a) Failure rate for switch $\left({\mathrm{S}}_{\mathrm{i}}\right)$: As per (5), the failure rate of the switch $\left({\mathrm{S}}_{\mathrm{i}}\right)$ can be calculated as
$ {\lambda }_{\mathrm{{si}}} = {\lambda }_{\mathrm{{si}},\text{ base }} \times \alpha {T}_{\mathrm{{si}}} = \times {\alpha Q} \times {\alpha A} \times {\alpha E} $
For the reliability calculation, the idea switches have been considered, hence ${\alpha A} = {\alpha Q} = 1$, and for same environmental condition for all the devices, it gives that ${\alpha E} = 1$. The base failure rate of the switch $\left({\lambda }_{\text{si, base }}\right)$ is taken as 0.00074. The ${\alpha T}$ for the switch and diode is given as
$ \alpha {T}_{\mathrm{{si}}} = \exp \left\lbrack {-{1925} \times \left({\frac{1}{{T}_{\mathrm{j}} + {273}} - \frac{1}{298}}\right) }\right\rbrack $
Where ${T}_{\mathrm{j}}$ is the junction temperature of the switch, which can be calculated as
$ {T}_{\mathrm{j}} = {T}_{\mathrm{c}} + {\theta }_{\mathrm{{jc}}} $
$ {T}_{\mathrm{c}} = {T}_{\mathrm{a}} + {\theta }_{\mathrm{{ca}}} \times {P}_{\text{loss }} $
Where ${T}_{\mathrm{c}}$ and ${T}_{\mathrm{a}}$ are the heat sink and ambient temperature, respectively. ${\theta }_{\mathrm{{jc}}}$ and ${\theta }_{\mathrm{{ca}}}$ are junction to case and case to ambient thermal impedances. The values of ${T}_{\mathrm{a}},{\theta }_{\mathrm{{jc}}}$ and ${\theta }_{\mathrm{{ca}}}$ are assumed as ${25}^{ \circ }\mathrm{C},{0.45}^{ \circ }\mathrm{C}/\mathrm{W}$ and ${62}^{ \circ }\mathrm{C}/\mathrm{W}$, respectively. ${P}_{\text{loss }}$ is the total power loss of the switch obtained from the PLECS real time simulator.
(a) Failure rate for capacitor $\left({C}_{\mathrm{i}}\right)$:
$ {\lambda }_{\mathrm{{ci}}} = {\lambda }_{\mathrm{{ci}},\text{ base }} \times {\alpha }_{\mathrm{{cv}}} \times {\alpha Q} \times {\alpha S} \times \alpha \mathrm{E} $
The ${\alpha }_{\mathrm{{cv}}}$ and ${\alpha S}$ for the capacitor is given as
$ {\alpha }_{\mathrm{{cv}}} = {0.34} \times {C}^{0.12},{\alpha }_{\mathrm{s}} = {V}_{\mathrm{s}}^{2.43} $
Where ${V}_{\mathrm{S}}$ is equal to the ratio of operating voltage to rated voltage and c is the capacitance in microfarad.
From the component’s failure rate, the overall system’s reliability can be evaluated using the Markov chain model. The reliability of the proposed 7L common ground FT inverter has been analyzed using the Markov chain model in two conditions of the inverter, without redundant switches and with redundant switches.
A. Reliability Without Redundant Switches
This section analyzes the failure rate of the inverter without redundant switches. In the event of a failure in any component, the whole system is completely shut down. It is assumed that each component will have two states to evaluate the reliability per the Markov chain process: operational state 1 and failure state 2. Fig. 6 shows the state transition diagram of the converter without redundant switches. It illustrates that the failure of any of the switches, i.e., ${\mathrm{T}}_{1} - {\mathrm{T}}_{11}\left({\mathop{\sum }\limits_{{i = 1}}^{{11}}{\lambda }_{\mathrm{{Si}}}}\right)$ or any of the capacitors, i.e., ${C}_{1} - {C}_{3}\left({\mathop{\sum }\limits_{{i = 1}}^{3}{\lambda }_{\mathrm{{ci}}}}\right)$ can lead to overall system failure. The ${P}_{1}\left(t\right)$ and ${P}_{2}\left(t\right)$ are occupations of probability in state 1 (operational) and state 2 (failed), respectively. Based on the state transition diagram of the inverter without redundant switches, the state equation can be written as [20]
$ \left\lbrack \begin{array}{ll} {P}_{1}\left(t\right) & {P}_{2}\left(t\right) \end{array}\right\rbrack = \left\lbrack \begin{array}{ll} {P}_{1}\left(t\right) & {P}_{2}\left(t\right) \end{array}\right\rbrack \left\lbrack \begin{matrix} - {\lambda }_{12} & {\lambda }_{12} \\ 0 & 0 \end{matrix}\right\rbrack $
Inverter is assumed to be functioning at $t = 0$, hence,
$ {P}_{1}\left(0\right) = 1,{P}_{2}\left(0\right) = 0 $
After solving the differential (12)
$ {P}_{1}\left(t\right) = {e}^{-{\lambda }_{12}t} $
Where ${\lambda }_{12}$ is the rate when state 1 the inverter makes the transition to state 2, which is defined as
$ {\lambda }_{12} = \mathop{\sum }\limits_{{i = 1}}^{{11}}{\lambda }_{\text{si }} + \mathop{\sum }\limits_{{i = 1}}^{3}{\lambda }_{\text{ci }} $
Substituting the value of ${\lambda }_{12}$ in (14) the occupation of probability in state 1, i.e., operational state ${P}_{1}\left(t\right)$ has been computed as
$ {P}_{1}\left(t\right) = \exp \left\lbrack {-\left({\mathop{\sum }\limits_{{i = 1}}^{{11}}{\lambda }_{\mathrm{{Si}}} + \mathop{\sum }\limits_{{i = 1}}^{3}{\lambda }_{\mathrm{{ci}}}}\right) t}\right\rbrack $
The procedure described in [20] calculates the switches and capacitors’ component failure rate $\left(\lambda \right)$. The reliability function of the inverter system without FT mode, is given by
$ R\left(t\right) = {P}_{1}\left(t\right) = {e}^{-{0.13.912t}} $
B. Reliability With Redundant Switches
Markov reliability analysis is also extended to evaluate the enhanced reliability of the suggested fault-tolerance circuit in comparison with base topology. The reliability of the inverter system with redundant switches has been assessed by considering its five different states.
State 1: Converter is in the complete operational state. State 2: One switch failure (1 SW). State 3: Two switches failure (2 SW). State 4: One capacitor failure (1 CAP). State 5: Two capacitors failure (2 CAP). State 6: Complete converter failure. Also, it has to be noted that when any of the components fails, it is replaced with a new switching strategy, according to Table II, at the same time. The replacement time is so short that it can be neglected. The Markov chain diagram of the inverter with the proposed fault tolerant scheme has been shown in Fig. 7. The corresponding occupational probability during fault is given as,
$ A = \left\lbrack \begin{matrix} - \left\lbrack {\lambda }_{{12},{13},{14},{15}}\right\rbrack & {\lambda }_{12} & {\lambda }_{13} & {\lambda }_{14} & {\lambda }_{15} & 0 & \\ 0 & - \left\lbrack {\lambda }_{{23},{26}}\right\rbrack & {\lambda }_{23} & 0 & 0 & {\lambda }_{26} & \\ 0 & 0 & - \left\lbrack {\lambda }_{{34},{36}}\right\rbrack & {\lambda }_{34} & 0 & {\lambda }_{36} & \\ 0 & 0 & 0 & 0 & - \left\lbrack {\lambda }_{{45},{46}}\right\rbrack & {\lambda }_{45} & {\lambda }_{46} \\ 0 & 0 & 0 & 0 & 0 & - {\lambda }_{56} & {\lambda }_{56} \\ 0 & 0 & 0 & 0 & 0 & 0 & 0 \end{matrix}\right\rbrack \left({18}\right) $
The various failure rates are given as follows:
$ \left\{ \begin{array}{l} {\lambda }_{12} = \left({\lambda }_{\mathrm{{SL}} - \mathrm{S}{12}}\right) {P}_{\mathrm{R}},{\lambda }_{13} = \left({\lambda }_{2\mathrm{{sw}}}\right) {P}_{\mathrm{R}},{\lambda }_{14} = \left({\lambda }_{\mathrm{C}1 - \mathrm{C}3}\right) {P}_{\mathrm{R}}, \\ {\lambda }_{15} = \left({\lambda }_{2\mathrm{{CAP}}}\right) {P}_{\mathrm{R}},{\lambda }_{23} = \left({{\lambda }_{\mathrm{{SL}} - {512}} + {\lambda }_{2\mathrm{{sw}}}}\right) {P}_{\mathrm{R}}, \\ {\lambda }_{34} = \left({{\lambda }_{2\mathrm{{sw}}} + {\lambda }_{\mathrm{{Cl}} - {23}}}\right) {P}_{\mathrm{R}},{\lambda }_{45} = \left({{\lambda }_{\mathrm{{Cl}} - {23}} + {\lambda }_{2\mathrm{{CAP}}}}\right) {P}_{\mathrm{R}}, \\ {\lambda }_{26} = \left({{\lambda }_{\mathrm{{SL}} - {512}} + {\lambda }_{2\mathrm{{sw}}}}\right) \left({1 - {P}_{\mathrm{R}}}\right),{\lambda }_{36} = \left({{\lambda }_{2\mathrm{{sw}}} + {\lambda }_{\mathrm{{Cl}} - {23}}}\right) \left({1 - {P}_{\mathrm{R}}}\right), \\ {\lambda }_{46} = \left({{\lambda }_{2\mathrm{{CAP}}} + {\lambda }_{\mathrm{{Cl}} - {23}}}\right) \left({1 - {P}_{\mathrm{R}}}\right),{\lambda }_{56} = \left({{\lambda }_{2\mathrm{{CAP}}}\left({1 - {P}_{\mathrm{R}}}\right) }\right), \end{array}\right. $
Where ${P}_{\mathrm{R}}$ is the probability of the satisfactory operation of the redundant switches, here, it is assumed ${P}_{\mathrm{R}} = {0.9}$.
After substituting various component failure rates in (7), the occupational probability function can be written as follows:
$ \left\lbrack {{P}_{1}\left(t\right) {P}_{2}\left(t\right) {P}_{3}\left(t\right) {P}_{4}\left(t\right) {P}_{5}\left(t\right) {P}_{6}\left(t\right) }\right\rbrack = \\ \left\lbrack {{P}_{1}\left(t\right) {P}_{2}\left(t\right) {P}_{3}\left(t\right) {P}_{4}\left(t\right) {P}_{5}\left(t\right) {P}_{6}\left(t\right) }\right\rbrack \times A $
$ {P}_{2}\left(t\right) = {55.25}\left({{e}^{-{0.1307t}} - {e}^{-{0.13912t}}}\right) $
$ {P}_{3}\left(t\right) = {2.467}{e}^{-{0.062t}} - {95.13}{e}^{-{0.131t}} + {92.66}{e}^{-{0.139t}} $
$ \begin{aligned} {P}_{4}\left(t\right) = & {2.344}{e}^{-{0.02786t}} - {4.3438}{e}^{-{0.0624t}} + {56.24}{e}^{-{0.10307t}} - \\ & {54.24}{e}^{0.1391t} \end{aligned} $
$ {P}_{5}\left(t\right) = {0.1990}{e}^{-{0.0053t}} - {0.4031}{e}^{-{0.02786t}} + {329}{e}^{-{0.0624t}} - $
The reliability function is
$ R\left(t\right) = {P}_{1}\left(t\right) + {P}_{2}\left(t\right) + {P}_{3}\left(t\right) + {P}_{4}\left(t\right) + {P}_{5}\left(t\right) $
$ R\left(t\right) = {0.1990}{e}^{-{0.53t}} + {1.940}{e}^{-{02.786t}} + {1.547}{e}^{-{06.24t}} + \\ {14.33}{e}^{-{013.07t}} - {13.92552}{e}^{-{13.91t}} $
Fig. 8 illustrates the reliability over the operational time of the proposed inverter in both without and with a FT scheme at ${25}^{ \circ }\mathrm{C}$, based on (17) and (25), respectively. The reliability curve at ${45}^{ \circ }\mathrm{C}$ and ${65}^{ \circ }\mathrm{C}$ ambient temperature with a FT scheme has also been shown to enhance the value of the proposed converter for various engineering applications. The FT inverter maintains higher reliability over time compared to the non-FT inverter at all temperatures due to the modified reference signal and the presence of redundant switches (TR1-TR4) $\left({{\mathrm{T}}_{\mathrm{R}1} - }\right.$ ${\mathrm{T}}_{\mathrm{R}4}$). As the temperature increases, the reliability of the FT inverter decreases, but it still performs better than the non-FT inverter. Thus, the proposed converter can work under single or multiple switch failure with improved reliability at varying ambient temperatures.
IV. Simulation and Hardware Validation
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The performance of the proposed FT 7L inverter was validated using Matlab/Simulink and a ${500}\mathrm{\;W}$ hardware prototype shown in Fig. 9. System parameters for both hardware and simulation are provided in Table III. Open circuit (OC) switch faults were categorized into three groups for analysis: single switch fault, double switch fault, and triple switch fault, with detailed analysis for each group presented.
A. Healthy 7L Inverter
The Fig. 10 shows the simulation and hardware results for the 7L inverter in healthy condition. It is observed that the phase voltage ${V}_{\mathrm{{AN}}}$ is nearly ${326}\mathrm{\;V}$ i.e., and top voltage level is almost thrice the inverter input voltage ${V}_{\mathrm{{dc}}}$. The RMS voltage and current values at the output are ${230}\mathrm{\;V}$ and ${2.1}\mathrm{\;A}$, respectively. Fig.11 shows that ${C}_{1},{C}_{2},{C}_{3}$ voltages are self-balanced during operation and maintaining the constant voltage across it.
B. Single Switch Fault
1) Fault on Switch ${T}_{2}$
Table II displays the fault tolerance analysis for different switches in the proposed inverter. It indicates in case of a malfunction of switch ${\mathrm{T}}_{2}$, the inverter can generate the full range of 7L voltages using redundant switches, similar to its healthy condition. Fig. 12 displays the simulation and practical waveforms for the switch ${\mathrm{T}}_{2}$ fault condition. The simulation and hardware results indicate that when a fault occurs in switch ${\mathrm{T}}_{2}$ at $t = {0.2}\mathrm{\;s}$ by withdrawing gate pulses ${\mathrm{G}}_{\mathrm{T}2}$, the output waveform exhibits only p(iac) (VAN) and discontinues current (iac) supply to the load. After clearing the fault at $t = {0.6}\mathrm{\;s}$, switch ${\mathrm{T}}_{2}$ is replaced with redundant switches ${\mathrm{T}}_{\mathrm{{Rl}}}$, receiving gate pulse ${\mathrm{G}}_{\mathrm{{TRl}}}$. The inverter consistently produces a 7L output voltage and supplies the load during the post-fault state. The consistent number of on-state switches in both pre-fault and post-fault states indicates unchanged efficiency in both conditions.
2) Fault on Switch ${T}_{3}$
The simulation and experimental waveform for the switch ${\mathrm{T}}_{3}$ fault condition are shown in Fig.13. It can be observed from the simulation and hardware results that when the fault occurs in switch ${\mathrm{T}}_{3}$ at $t = {0.2}\mathrm{\;s}$ by with drawing gate pulses ${\mathrm{G}}_{\mathrm{T}3}$ from it, the output waveform during the post-fault state, i.e., after clearing the fault at $t = {0.26}\mathrm{\;s}$, the inverter switch ${\mathrm{T}}_{3}$ has been replaced with the redundant switches ${\mathrm{T}}_{\mathrm{R}2}$, and the gate pulse ${\mathrm{G}}_{\mathrm{{TR}}2}$ is given to it. The inverter continues to generate $7\mathrm{\;L}$ output voltage and supply to the load, as in healthy cases, pre-fault and post-fault efficiencies remain the same. The faults in switches ${\mathrm{T}}_{10}$ and ${\mathrm{T}}_{11}$ can be analyzed like those in switches ${\mathrm{T}}_{2}$ and ${\mathrm{T}}_{3}$.
3) Fault on Switch ${T}_{5}$
Switch ${\mathrm{T}}_{5}$ is an essential for charging ${C}_{2}$, and voltage level $\pm$ $3{V}_{\mathrm{{dc}}}$ is not possible to generate at the output. Notably, applying a modified reference signal, as shown in Fig. 2 (b), results in a $5\mathrm{\;L}$ output voltage $\left({\pm 2{V}_{\mathrm{{dc}}}, \pm {V}_{\mathrm{{dc}}},0}\right)$ during post-fault operation. If ${\mathrm{T}}_{5}$ experiences a fault, the output voltage level changes from seven to five levels, as illustrated in the simulation and experimental results shown in Fig. 14. Despite a slight reduction in power output, the inverter continues to supply power to the load.
C. Double Switch Fault
Fault on switch ${\mathrm{T}}_{4}$ and ${\mathrm{T}}_{6}$ simultaneously: The inverter circuit operation reveals that the switch ${\mathrm{T}}_{4}$ and ${\mathrm{T}}_{6}$ are essential for charging ${C}_{1}$ and ${C}_{2}$. When a fault occurs in switch ${\mathrm{T}}_{4}$ and ${\mathrm{T}}_{6}$ at the time $t = {1.9}\mathrm{\;s}$ by removing the gate pulse （G4 and G6), the inverter will shut down based on the discharge time of the three SCs. The PWM reference signal needs to be modified as in Fig. 2(c).
To maintain the continuity to supply sinusoidal voltage (VAN) and current $\left({i}_{\mathrm{{ac}}}\right)$ of load. Three output voltage $\left({V}_{\mathrm{{AN}}}\right)$ levels, i.e, $\left({0, \pm {\mathrm{V}}_{\mathrm{{dc}}}}\right)$, can be generated with a modified PWM reference signal to continue the supply to the load, as shown in the simulation and hardware results in Fig. 15. Similarly, the simultaneous Fault on switches ${\mathrm{T}}_{2}$ and ${\mathrm{T}}_{3}$ can be analyzed as shown in the simulation and hardware results in Fig. 16.
D. Triple Switch Fault
Fault on switch ${\mathrm{T}}_{2},{\mathrm{\;T}}_{3}$ and ${\mathrm{T}}_{4}$ simultaneously: Fig. 17 presents the simulation and experimental results for the scenario in which switches ${\mathrm{T}}_{2},{\mathrm{\;T}}_{3}$, and ${\mathrm{T}}_{4}$ fail simultaneously. Both simulation and practical outcomes reveal that, by changing the PWM reference signal and replacing switches ${\mathrm{T}}_{2}$ and ${\mathrm{T}}_{3}$ with the redundant switches ${\mathrm{T}}_{\mathrm{R}2}$ and ${\mathrm{T}}_{\mathrm{R}3}$ as outlined in Table II, a $5\mathrm{\;L}$ voltage, i.e., $\pm 2{V}_{\mathrm{{dc}}}, \pm {V}_{\mathrm{{dc}}},0$ can be generated at the output.
V. Voltage, Current Stress and Loss Analysis
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The detail analysis of voltage and current stress for each switch and capacitor for a 7L operation of the proposed inverter is tabulated in Table IV. From which it can be noticed that switches ${\mathrm{T}}_{2},{\mathrm{\;T}}_{3},{\mathrm{\;T}}_{10}$, and ${\mathrm{T}}_{11}$ have voltage stress three times the input voltage, while switches ${\mathrm{T}}_{1}$, and ${\mathrm{T}}_{5}$ have voltage stress nearly two times the input voltage. In contrast, the remaining switches and all the three capacitors (C1,C2 and C3) have voltage stress almost the same as the input voltage of ${V}_{\mathrm{{dc}}}$. The current stress profile of all the involved power switches for the proposed inverter has also been listed in Table IV, which revealed that four power switches of ${\mathrm{T}}_{1},{\mathrm{\;T}}_{1},{\mathrm{\;T}}_{10}$, and ${\mathrm{T}}_{11}$ are tolerating the maximum current stress equal to around $4{I}_{\max }$ whereas switch ${\mathrm{T}}_{4},{\mathrm{\;T}}_{9}$ and capacitor ${\mathrm{C}}_{1}$ has current of $2{I}_{\max }$, all other switches and capacitors are having current stress almost equal to the peak output current ${I}_{\max }$, i.e.
The conduction (Pcond) and switching (Psw) loss distribution for the proposed inverter for healthy and all the fault conditions has been shown in Fig. 18. It can be observed that during healthy condition and 7L voltage post-fault condition, the power loss in the switches ${\mathrm{T}}_{1},{\mathrm{\;T}}_{10}$, and ${\mathrm{T}}_{11}$ are slightly higher due to higher current and voltage stress. Meanwhile, in 5L and $3\mathrm{\;L}$ output cases, ${\mathrm{T}}_{\mathrm{R}1},{\mathrm{T}}_{\mathrm{R}2},{\mathrm{T}}_{\mathrm{R}3},{\mathrm{\;T}}_{\mathrm{R}4}$ and ${\mathrm{T}}_{9}$ switches have to undergo higher losses than other switches as they have high conduction time during fault. Fig. 19 illustrates the efficiency versus modulation index for the proposed inverter under healthy condition and post-fault output voltages at $7\mathrm{\;L},5\mathrm{\;L}$, $3\mathrm{\;L}$ conditions. During the $7\mathrm{\;L}$ post-fault output, the inverter maintains efficiency comparable to healthy conditions in other it is slightly less.
VI. MPPT Approach for the Proposed Inverter
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The block diagram for the complete MPPT control system is shown in Fig. 20 [27], [28]. The PV voltage (Vdc) and current (Idc) are measured, and the perturb and observe (P&O) MPPT algorithm is applied to extract the maximum power from the PV system. The MPPT controller generates a ${I}_{\text{ref }}$ signal, which is fed to the PR controller. The PR controller regulates the proposed CG-FT MLI’s output voltage during varying environmental conditions and generates the gate pulses for the inverter. To verify operation of the proposed inverter in varying environmental conditions, the system is simulated in Matlab environment. ASM-M12-132-AAA-650 is selected from the Eternal Pride Series manufactured by Adani Solar for evaluating the functionality of the suggested converter and the power rating of the PV panel considered as ${1500}\mathrm{\;W},\mathrm{{OC}}$ voltage as ${45.12}\mathrm{\;V}$ and short circuit current as ${9.36}\mathrm{\;A}$. The five PV modules are connected in series, and one module is connected in parallel. Fig. 21 (a) illustrates the step change in temperature from ${60}^{ \circ }\mathrm{C}$ to ${1}^{ \circ }\mathrm{C}$. Correspondingly, PV terminal voltage has been changed.
To ensure the constant grid voltage irrespective of temperature changes, the modulation index $\left({M}_{\mathrm{i}}\right)$ of the inverter is altered from 0.65 to 0.85. Furthermore, Fig. 21(b) illustrates the step change in insolation from ${100}\mathrm{\;W}/{\mathrm{m}}^{2}$ to ${1000}\mathrm{\;W}/{\mathrm{m}}^{2}$. Correspondingly, the PV current has changed significantly from 2 A to 5 A. As the modulation index is constant, the voltage remains constant. Further, the designed current controller effectively injects the current to the AC grid as per the insolation characteristics of the PV string. As the time required to track the MPPT is significantly longer than the inverter’s switching period, it ensures the capacitors have sufficient time to charge before the next tracking cycle. Hence, MPPT has been achieved, and the proposed system is a suitable transformerless PV inverter system that boosts and reduces leakage current for grid-connection applications.
VII. Comparative Analysis
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A comparative assessment has been conducted to highlight the uniqueness of the proposed converter in two ways, i.e., 1) Comparative analysis between the proposed inverter with other recent FT topologies. 2) Comparative analysis between the proposed inverter with traditional H-bridge inverter topologies. It is worth noting that the presented work has a common ground feature that distinguishes it from other fault-tolerant inverters in the literature. Tables V and Table VI summarized the comparative analysis for recent FT and traditional H-bridge topology, respectively. Each attribute is detailed as follows.
A. Comparative Analysis Between the Proposed Inverter With Other Recent FT Topologies
1) Components Count $\left({{N}_{\text{sw.}}{N}_{\mathrm{D}},{N}_{\mathrm{{sr}}},{N}_{\mathrm{c}}\text{and}{N}_{\mathrm{{dc}}}}\right)$
The component count is an essential criterion for selecting any inverter for a given application. Table V compares the proposed inverter with the other FT inverters in recent literature, based on the number of switches $\left({N}_{\mathrm{{sw}}}\right)$, redundant switches $\left({N}_{\mathrm{{sr}}}\right)$, diodes $\left({N}_{\mathrm{D}}\right)$, capacitors $\left({N}_{\mathrm{c}}\right),\mathrm{{DC}}$ source $\left({N}_{\mathrm{{dc}}}\right)$ requirements. The proposed converter has fewer component counts than [22] and [23]. However, the other features, such as static, zero leakage current, and self-voltage balancing, make it a unique inverter.
2) Leakage Current Handling Capabilities
The proposed converter has distinguished characteristics of negligible leakage current due to the common ground between source and load. This makes it unique from other 7L FT inverters in the recent literature. These features validate the suitability of the proposed inverter for PV applications.
3) Control Complexity
The proposed FT inverter has self-voltage balancing across SCs and negligible leakage current during pre-fault and post-fault periods. Hence, no extra circuitry or control strategy is needed to balance the capacitor voltages. Hence, the control complexity of the proposed topology is the least among the available FT MLI topologies.
4) TSV and CF
An inverter’s capabilities cannot be justified only by its component count. The device rating is also an important parameter for selecting any converter for an application, which affects the cost of the inverter. It can be seen that the proposed topology has the least TSV as compared to other FT inverters. For a fair evaluation of the costs associated with different fault-tolerant multilevel inverters (FTMLIs), a CF detailed in [24] - [26] has been considered.
$ {CF} = \frac{{N}_{\mathrm{{dc}}}}{{N}_{\mathrm{L}}} \times \left\lbrack {{N}_{\mathrm{{SW}}} + {N}_{\mathrm{D}} + {N}_{\mathrm{{SR}}} + {N}_{\mathrm{C}} + \left(\frac{\alpha \times {TS}{V}_{\mathrm{{PU}}}}{\beta }\right) }\right\rbrack $
Here, $\alpha$ and $\beta$ constants provide flexibility in weighting the significance of device count and TSV. The proposed topology’s cost, is influenced by component count. A higher number of DC sources (Ndc) complicates voltage compatibility and isolation, impacting cost. The costs rise with more DC sources but decrease with more output voltage levels (NL). The proposed topology achieves a 7L output with just one DC source, lowering its cost compared to other FT inverters in the literature.
5) Reliability of the Inverter
The previous section extensively analyzed the reliability of the proposed inverter, expressed by the reliability function (19). Comparative reliability calculations were also performed for the topology in references [13], [14], [16], [22]. The reliability plot in Fig. 22 indicates that the proposed inverter surpasses the referenced inverters in reliability. It exhibits tolerance to single and multiple switch faults with minimal modifications to the modulation scheme.
B. Comparative Analysis Between the Proposed Inverter With Traditional H-Bridge Inverter Topologies
To show the compatibility of the proposed inverter with traditional $\mathrm{H}$ -bridge inverter, a thorough comparison of the proposed inverter with traditional $3\mathrm{\;L}$ and $7\mathrm{\;L}\mathrm{H}$ -bridge inverters integrated with a front-end boost converter has been carried out and tabulated in Table VI. It is noticed that the proposed FT inverter has the least CF as compared to the traditional H-bridge inverters by considering different parameters as (19). The traditional H-bridge based 3L inverter shows higher efficiency and lower component count. Also, the 7L H-bridge inverter requires a higher component count to realize the multi-level operation, which results in the lowest efficiency. Moreover, both the above-said topologies suffer from the issue of leakage current due to PV parasitic capacitance. They cannot be used directly for PV applications as per the German VDE 0126-1-1 standard. Further, the proposed inverter has FT capability and high reliability.
VIII. Conclusion
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This paper introduces a 7L switched capacitor-based FT inverter with a common ground. This inverter showcases advanced capabilities, such as eliminating leakage current, self-balancing SC voltages, boosting voltage in regular, and FT modes, setting it apart with unique features. The reliability of the converter has been rigorously assessed through a Markov chain approach to reliability analysis.
Integrating redundant switches enhances fault tolerance and significantly elevates the overall reliability of the inverter compared to counterparts lacking such redundancy. The results explicitly confirm its superiority through comprehensive simulation and hardware testing, particularly in photovoltaic system-based inverter applications connected to loads requiring a continuous power supply. This research contributes valuable insights and practical advancements to power electronics and FT systems.
ACKNOWLEDGMENT
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The authors would like to acknowledge Power System and Smart Grid Research Laboratory, Dept. of EEE, NIT Tiruchirappalli for their support to carryout this work.
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Appendix
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Year 2025 volume 10 Issue 1
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Cite this Article
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Article Info
doi: 10.24295/CPSSTPEA.2025.00002
  • Receive Date：2024-05-15
  • Online Date：2025-07-05
  • Published：2025-03-10
Article Data
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History
  • Received：2024-05-15
  • Revised：2024-12-04
  • Accepted：2025-01-03
Affiliations
    1 National Institute of Technology Tiruchirappalli Tiruchirappalli 620015 India
    2 B.M.S. College of Engineering Bangalore 560019 India
    3 National Institute of Technology Rourkela Rourkela 769008 India
    4 National Institute of Technology Tiruchirappalli Electrical Engineering Department Tiruchirappalli 620015 India
    5 University of Technology Sydney Sydney 2007 Australia

Corresponding:

Sateesh Kumar Kuncham.
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表12种不同金属材料的力学参数
科
Family		 属数
Number of
genus		 种数
Number of
species		 占总种数比例
Percentage of
total species (%)		 属
Genus		 种数
Number of
species		 占总种数比例
Percentage of total
species (%)
鹅膏菌科Amanitaceae 2 11 5.26 鹅膏菌属 Amanita 10 4.78
小菇科 Mycenaceae 2 12 5.74 丝盖伞属 Inocybe 5 2.39
多孔菌科 Polyporaceae 8 14 6.70 蜡蘑属 Laccaria 5 2.39
红菇科 Russulaceae 3 23 11.00 小皮伞属 Marasmius 6 2.87
小菇属 Mycena 11 5.26
光柄菇属 Pluteus 5 2.39
红菇属 Russula 17 8.13
栓菌属 Trametes 5 2.39
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