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An Improved Finite Control Set Model Predictive Control Based on a Novel Dual-Port Three-Level Inverter
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Guifeng WANG, Xin YUAN, Yunhui JIANG, Jianfei WANG, Fei WANG, Zhan LIU
CPSS Transactions on Power Electronics and Applications | 2024, 9(4) : 430 - 442
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CPSS Transactions on Power Electronics and Applications | 2024, 9(4): 430-442
• Original articles •
An Improved Finite Control Set Model Predictive Control Based on a Novel Dual-Port Three-Level Inverter
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Guifeng WANG, Xin YUAN, Yunhui JIANG, Jianfei WANG, Fei WANG, Zhan LIU
Affiliations
  • Jiangsu Normal University College of Electrical Engineering and Automation Xuzhou 221116 China

    • Guifeng Wang was born in Linyi, Shandong, China, in 1982. He obtained his B.S. degree in electrical engineering and automation and M.S. degree in electrical engineering from the School of Information and Electrical Engineering, China University of Mining and Technology, Xuzhou, China, in 2004 and 2007, respectively. In 2016, he was awarded a Ph.D. degree in power electronics and electrical drive from Shanghai Jiao Tong University, Shanghai, China. Currently, Dr. Wang holds the position of Senior Engineer at the College of Electrical Engineering and Automation, Jiangsu Normal University, Xuzhou. His research interests include power electronic converters for electrical drives and power quality enhancement.

    Xin Yuan, born in Shanxi, China, in 2000, received her B.S. degree from Jiangsu Normal University, Xuzhou, China, in 2018. She is presently pursuing a master's degree in the School of Electrical Engineering and Automation at Jiangsu Normal University, Xuzhou, China. Her current research interests include power electronic converters and model predictive current control techniques.

    Yunhui Jiang, born in Nantong, China, in 1998, received his B.S. degree from Jiangsu Ocean University, Lianyungang, China, in 2017. He is currently pursuing a master's degree in the School of Electrical Engineering and Automation at Jiangsu Normal University, Xuzhou, China. His research interests include power electronics and electric machine drives.

    Jianfei Wang, born in Suichuan, China, in 2000, obtained his B.S. degree in electrical engineering and automation from Nanchang Hangkong University in 2022. He is currently pursuing an M.S. degree in electronic information at Jiangsu Normal University, Xuzhou, China. His research interests include centered on power electronic converter design and model predictive current control techniques.

    Fei Wang received his M.S. degree in electrical engineering from the School of Information and Electrical Engineering, China University of Mining and Technology, Xuzhou, China, in 2009. He currently serves as a Laboratory Teacher in the School of Electrical Engineering and Automation at Jiangsu Normal University, Xuzhou, China. His research interests include power systems and new energy power generation technology.

    Zhan Liu obtained his B.S., M.S., and Ph.D. degrees from the School of Information and Electrical Engineering at China University of Mining and Technology, Xuzhou, China, in 2004, 2007, and 2016, respectively. He is currently employed as a Faculty Member in the School of Electrical Engineering and Automation at Jiangsu Normal University, Xuzhou, China. His research interests include power electronics, modern control theory, and multilevel converters.

Published: 2024-12-10 doi: 10.24295/CPSSTPEA.2024.00027
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In response to the high cost and large size issues associated with traditional backtoback threelevel inverters, this paper proposes a novel dualport threelevel inverter (DPTLI) that simplifies the system structure through the utilization of switch multiplexing. Based on the proposed inverter topology, a timesharing coordination finite control set model predictive control (TSCFCSMPC) strategy is developed. The strategy, grounded in the concept of timesharing control, incorporates a coordinated approach within a twocycle control loop. During the first cycle, the primary control objective is to optimize the output current of the upper port, with the selection of the optimal vector centered around this goal. Subsequently, the lower port's output is coordinated through control, leveraging the unique aspects of switch multiplexing and the redundancy in switch states inherent in the proposed topology. In the second cycle, the emphasis is reversed, with the optimization of the lower port's output current taking precedence, while the upper port is subjected to coordinated control. The implementation of this method significantly enhances the quality of the output current and the overall efficiency of the system. The viability and effectiveness of both the proposed topology and the control strategy are confirmed through simulation and experimental results.

Dual-port  /  finite control set model predictive control (FCS-MPC)  /  inverter  /  switch multiplexing  /  time-sharing coordination
Guifeng WANG, Xin YUAN, Yunhui JIANG, Jianfei WANG, Fei WANG, Zhan LIU. An Improved Finite Control Set Model Predictive Control Based on a Novel Dual-Port Three-Level Inverter[J]. CPSS Transactions on Power Electronics and Applications, 2024 , 9 (4) : 430 -442 . DOI: 10.24295/CPSSTPEA.2024.00027
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I. INTRODUCTION
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THE multiplexed dual-output inverter has demonstrated significant advantages over traditional back-to-back inverters, including a reduced number of switches, lower production costs, and a more compact size. This innovative technology has been successfully implemented in various applications, such as wind power generation systems [1]-[3], high-power traction systems [4]-[6], and unified power quality regulators [7]-[9].
The nine-switch converter (NSC) employs switch multiplexing to minimize the number of switches [7], enabling AC outputs at two ports [10]. However, this topology is constrained by several limitations, including higher voltage stress on the switches, fewer output levels, and increased harmonic generation. These drawbacks restrict its application in high-power and high-direct current voltage scenarios [11],[12].
Multi-level inverters offer distinct advantages over their two-level counterparts, including an increased number of output levels, enhanced output waveform quality, and reduced voltage stress and switching losses on the switches [13]. J. Haruna proposed a three-level twin drive inverter (TL-TDI), which produces two sets of three-phase AC outputs using 21 power switches [14]. However, this topology subjects the common switches to high voltage stress. Professor Wang Rutian’s team at Northeast Electric Power University introduced a three-phase dual-output neutral point-clamped three-level inverter (DO-NPC-TLI), comprising 20 switches and 12 diodes. This design halves the voltage stress across all power switches to half of the DC link voltage. Nevertheless, the topology’s inherent limitations prevent independent control of the upper and lower output ports [15]. The team also developed a novel dual-output T-type three-level inverter (DO-T-TLI), which integrates the T-type three-level topology with the NSC topology to control two independent loads. However, a larger number of switches in this design bear the full DC link voltage [16]. In [17], a five-leg, three-level dual-output inverter (5-leg, 3-level DOI) was proposed, based on two F-type inverters [18]. This design shares one phase leg between the two inverters, ensuring three-phase voltage outputs at both output ports and independent output for each phase.
Modulation strategies for multiplexed dual-output inverters primarily encompass carrier-based pulse width modulation (PWM)[19],[20], space vector modulation (SVM)[22]-[24], and finite control set model predictive control (FCS-MPC)[25]-[27]. FCS-MPC has garnered significant attention in power electronics research due to its simplicity in implementation, rapid dynamic response, and ease in achieving coordinated control of multiple objectives. In [28], FCS-MPC was first applied to NSC, utilizing the sum of the absolute values of current tracking errors at the upper and lower output ports as the cost function. However, this approach involves a substantial computational load due to 27 optimizations in each rolling step. To address the high ripple values in FCS-MPC for NSC generation drive applications,[29] proposed a duty cycle optimization decoupled predictive current control method. This approach reduces the computational load of the coupled section and achieves low-ripple technology for NSC generation. In [30], FCS-MPC was applied to a three-phase, three-level dual-output inverter, enabling output control at the dual output ports with different amplitudes, frequencies, and phase angles. This development laid the foundation for the subsequent advancement of FCS-MPC in three-level dual-output topologies.
This paper introduces a novel DP-TLI topology that simplifies the structure through switch multiplexing. Based on the characteristics of this topology, a time-sharing coordinated control finite control set model predictive control (TSC-FCS-MPC) method is proposed. This innovative approach enhances the quality of the output current and improves the overall efficiency of the system operation.
The structure of this paper is organized as follows: Initially, a comprehensive analysis of the DP-TLI topology and its operating principle is presented. Subsequently, the TSC-FCS-MPC strategy is introduced, which is tailored to the topology’s characteristics. This strategy encompasses the establishment of current prediction models and cost functions for both upper and lower ports, the formulation of voltage vector selection rules, and the development of a time-sharing coordinated control mechanism. The efficacy of the proposed topology and control strategy is then validated through extensive simulations and experimental studies. This paper concludes with a summary of primary contributions and innovative aspects of this research.
II. DP-TLI TOPOLOGY AND OPERATING PRINCIPLE
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A. DP-TLI Topology
The proposed DP-TLI topology is illustrated in Fig. 1. The topology consists of three phases (a, b, and c), with each phase comprising six power switches, denoted as ${\mathrm{S}}_{xi}$, where $x \in \{\mathrm{a},\mathrm{b}$, $\mathrm{c}\}, j \in \{ 1,2,\ldots ,6\}$, and one bidirectional switch ${\mathrm{S}}_{x7}$ connects to the DC side. The output ports are connected to resistive-inductive loads, characterized by inductances ${L}_{1}$ and L2, and resistances ${R}_{1}$ and ${R}_{2}$ for the upper and lower ports, respectively. The upper port’s output phase voltages $\left({{v}_{\mathrm{{UO}}},{v}_{\mathrm{{VO}}}}\right.$, and $\left.{v}_{\mathrm{{WO}}}\right)$ are measured at nodes U, V, and W with respect to the midpoint O, with corresponding output load currents ${i}_{\mathrm{{UVW}}}$. Similarly, the lower port’s output phase voltages $\left({{v}_{\mathrm{{XO}}},{v}_{\mathrm{{YO}}}}\right.$, and $\left.{v}_{\mathrm{{ZO}}}\right)$ are measured at nodes X, Y, Z, with output load currents ${i}_{\mathrm{{XYZ}}}$. The total DC link voltage is denoted as ${V}_{\mathrm{{dc}}}$, with capacitors ${C}_{1}$ and ${C}_{2}$. In addition, it is noteworthy that the series connection of power switches ${\mathrm{S}}_{x1}$ and ${\mathrm{S}}_{x2},{\mathrm{\;S}}_{x5}$ and ${\mathrm{S}}_{x6}$ may present voltage unbalancing issues in practical applications, which is a limitation of this topology. While the primary focus of this paper is to analyze and verify the topology’s feasibility using idealized switches, and future research will address the series equalization problem in detail.
B. Operating Principle
The topology’s inherent constraints dictate that output pins can’t be left floating and the DC bus mustn’t be short-circuited. Consequently, 6 valid switching states are possible for the output, as delineated in Table I. In this representation,“1” indicates an ON switch,“O” indicates an OFF switch, while “P”,“O”, and “N” represent output voltages of ${V}_{\mathrm{{dc}}}/2,0$, and $-{V}_{\mathrm{{dc}}}/2$, respectively. Owing to the symmetry of the three phases, phase a is used to illustrate the specific current flow paths for the six valid switching states, as depicted in Fig. 2. The upper output load current $\left({i}_{\mathrm{U}}\right)$ flow path is indicated by red lines, while the lower output load current $\left({i}_{\mathrm{X}}\right)$ flow path is denoted by blue lines. Analysis reveals that the topology imposes a constraint where the upper output voltage cannot be less than the lower output voltage.
C. Voltage Stress of Switches
An analysis of the voltage stress across each power switch is conducted based on the following assumptions:
(1) The voltage drop across simultaneously conducting power switches ${\mathrm{S}}_{\mathrm{a}1}$ and ${\mathrm{S}}_{\mathrm{a}2}$, as well as ${\mathrm{S}}_{\mathrm{a}5}$ and ${\mathrm{S}}_{\mathrm{a}6}$, is identical.
(2) The DC bus voltage remains constant. The maximum voltage stress across each switch is determined to be ${V}_{\mathrm{{dc}}}/2$. A comparative analysis of the proposed topology with existing literature is presented in Table II. The proposed DP-TLI achieves dual-port output while reducing the number of switches, with all switches experiencing voltage stress equal to half of the DC link voltage. This configuration significantly reduces the system’s size and cost.
III. TSC-FCS-MPC METHOD
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A. Traditional FCS-MPC Operating Principle
1)Mathematical Modeling
The traditional FCS-MPC methodology comprises three primary components: prediction model, overall optimization, and feedback correction. Initially, based on the sampling value at time $k$ and the established discretized mathematical model of the object, multiple possible output trajectories of the controlled object at time $\left({k + 1}\right)$ are derived. Subsequently, a cost function is employed to optimize the desired target, determining the switch state that minimizes the error between the system’s output at time $\left({k + 1}\right)$ and the given value. Through continuous iteration of this process, overall system optimization is achieved. Fig. 3 illustrates the structure block diagram of the inverter FCS-MPC control system.
To model and analyze the proposed topology, the dynamic models of the upper and lower ports are represented as follows:
$\left\{\begin{array}{l}{v}_{\mathrm{{up}}}\left(k\right)= {i}_{\mathrm{{up}}}\left(k\right){R}_{1}+ {L}_{1}\frac{\mathrm{d}{i}_{\mathrm{{up}}}\left(k\right)}{\mathrm{d}t}\\{v}_{\mathrm{{low}}}\left(k\right)= {i}_{\mathrm{{low}}}\left(k\right){R}_{2}+ {L}_{2}\frac{\mathrm{d}{i}_{\mathrm{{low}}}\left(k\right)}{\mathrm{d}t}\end{array}\right.$
where ${v}_{\mathrm{{up}}}\left(k\right)$ and ${v}_{\text{low }}\left(k\right)$ denote the three-phase voltage output from the upper and lower ports at moment $k$, and ${i}_{\mathrm{{up}}}\left(k\right)$ and ${i}_{\text{low }}\left(k\right)$ represent their corresponding output currents. The above equation is subjected to Clark transformation to obtain a simplified model of the inverter in the ${\alpha \beta }$ rotating coordinate system:
$\left\{\begin{array}{l}{v}_{\mathrm{{up}}\alpha }\left(k\right)= {i}_{\mathrm{{up}}\alpha }\left(k\right){R}_{1}+ {L}_{1}\frac{\mathrm{d}{i}_{\mathrm{{up}}\alpha }\left(k\right)}{\mathrm{d}t}\\{v}_{\mathrm{{up}}\beta }\left(k\right)= {i}_{\mathrm{{up}}\beta }\left(k\right){R}_{2}+ {L}_{2}\frac{\mathrm{d}{i}_{\mathrm{{up}}\beta }\left(k\right)}{\mathrm{d}t}\end{array}\right.$
$\left\{\begin{array}{l}{v}_{\text{low }\alpha }\left(k\right)= {i}_{\text{low }\alpha }\left(k\right){R}_{1}+ {L}_{1}\frac{\mathrm{d}{i}_{\text{low }\alpha }\left(k\right)}{\mathrm{d}t}\\{v}_{\text{low }\beta }\left(k\right)= {i}_{\text{low }\beta }\left(k\right){R}_{2}+ {L}_{2}\frac{\mathrm{d}{i}_{\text{low }\beta }\left(k\right)}{\mathrm{d}t}\end{array}\right.$
where ${T}_{\mathrm{s}}$ represents the sampling period, and ${i}_{\mathrm{{up}}\alpha ,\beta }\left(k\right)$, ${i}_{\text{low }\alpha ,\beta }\left(k\right)$ denote the current values output from the two ports in the ${\alpha \beta }$ rotational coordinate system.
$\left\{\begin{array}{l}{i}_{\mathrm{{up}}\alpha }\left({k + 1}\right)= \left({1 -\frac{{R}_{1}{T}_{\mathrm{s}}}{{L}_{1}}}\right){i}_{\mathrm{{up}}\alpha }\left(k\right)+ \frac{{T}_{\mathrm{s}}}{{L}_{1}}{v}_{\mathrm{{up}}\alpha }\left(k\right)\\{i}_{\mathrm{{up}}\beta }\left({k + 1}\right)= \left({1 -\frac{{R}_{1}{T}_{\mathrm{s}}}{{L}_{1}}}\right){i}_{\mathrm{{up}}\beta }\left(k\right)+ \frac{{T}_{\mathrm{s}}}{{L}_{1}}{v}_{\mathrm{{up}}\beta }\left(k\right)\end{array}\right.$
$\left\{\begin{array}{l}{i}_{\mathrm{{low}}\alpha }\left({k + 1}\right)= \left({1 -\frac{{R}_{2}{T}_{\mathrm{s}}}{{L}_{2}}}\right){i}_{\mathrm{{low}}\alpha }\left(k\right)+ \frac{{T}_{\mathrm{s}}}{{L}_{2}}{v}_{\mathrm{{low}}\alpha }\left(k\right)\\{i}_{\mathrm{{low}}\beta }\left({k + 1}\right)= \left({1 -\frac{{R}_{2}{T}_{\mathrm{s}}}{{L}_{2}}}\right){i}_{\mathrm{{low}}\beta }\left(k\right)+ \frac{{T}_{\mathrm{s}}}{{L}_{2}}{v}_{\mathrm{{low}}\beta }\left(k\right)\end{array}\right.$
2)Establishment of the Value Function
Building upon the established mathematical model, with current constraint variables as target variables, a model predictive controller for the proposed inverter is developed. The traditional FCS-MPC strategy constructs a cost function based on the sum of the absolute values of the errors between the reference values and the predicted values of the dual-output load currents:
$ g =\left|{{i}_{\mathrm{{up}}\alpha }^{* }\left({k + 1}\right)- {i}_{\mathrm{{up}}\alpha }\left({k + 1}\right)}\right|+ \left|{{i}_{\mathrm{{up}}\beta }^{* }\left({k + 1}\right)- {i}_{\mathrm{{up}}\beta }\left({k + 1}\right)}\right|+ \\\left|{{i}_{\mathrm{{low}}\alpha }^{* }\left({k + 1}\right)- {i}_{\mathrm{{low}}\alpha }\left({k + 1}\right)}\right|+ \left|{{i}_{\mathrm{{low}}\beta }^{* }\left({k + 1}\right)- {i}_{\mathrm{{low}}\beta }\left({k + 1}\right)}\right|\left(6\right)$
where ${i}_{\mathrm{{up}}\alpha ,\beta }^{* }\left({k + 1}\right)$ and ${i}_{\mathrm{{low}}\alpha ,\beta }^{* }\left({k + 1}\right)$ represent the reference values of upper and lower output currents at moment $\left({k + 1}\right)$.
With each phase having switch combinations as shown in Table I, the proposed inverter exhibits ${6}^{3}= {216}$ possible switching states. The controller must perform 216 optimizations within one control cycle to select the switching state that minimizes the cost function. This optimal state is then applied in the subsequent control instance to achieve optimal output control of the inverter. This method necessitates simultaneous consideration of the output effects of both upper and lower port currents, resulting in a substantial computational load for the controller within one control cycle.
B. Time-Sharing Operating Principle
To reduce the controller’s prediction operations and achieve independent control of the two ports in DP-TLI, a time-sharing finite control set model predictive control (TS-FCS-MPC) method is proposed. This method alternates between two operating modes: in the first control cycle (Mode 1), the lower port operates while the upper port remains at $+{V}_{\mathrm{{dc}}}/2$ ; in the subsequent control cycle (Mode 2), the upper port operates while the lower port remains at $-{V}_{\mathrm{{dc}}}/2$. These two cycles are continuously alternated for control. Fig. 4 illustrates the two operating modes for phase a, and Table III delineates the output states of the two ports.
The $\left({k + 1}\right)$ moment output currents of the upper and lower ports based on discrete time are represented by (4) and (5). Additionally, considering the dynamic model of the DC side capacitance, the capacitance current is expressed as:
${i}_{{C}_{n}}\left(t\right)= {C}_{n}\frac{\mathrm{d}{v}_{{C}_{n}}}{\mathrm{\;d}t}$
where $n \in \{ 1,2\}$ and ${C}_{n}$ idenotes the upper and lower bus capacitance value. Discretization is performed using the forward Euler method to obtain the discrete-time based DC side capacitance voltage:
${v}_{{C}_{n}}\left({k + 1}\right)= {v}_{{C}_{n}}\left(k\right)+ \frac{{T}_{\mathrm{s}}}{{C}_{n}}{i}_{{C}_{n}}\left(k\right)$
The time-sharing control enables independent control of the upper and lower ports. Considering the DC bus midpoint balance, an additional term representing the midpoint potential difference is incorporated. The value function ${g}_{1}$ for the upper port is constructed as:
${g}_{1}= \left|{{i}_{\mathrm{{up}}\alpha }^{* }\left({k + 1}\right)- {i}_{\mathrm{{up}}\alpha }\left({k + 1}\right)}\right|+ \left|{{i}_{\mathrm{{up}}\beta }^{* }\left({k + 1}\right)- {i}_{\mathrm{{up}}\beta }\left({k + 1}\right)}\right|+ \\\lambda \left|{{v}_{C1}\left({k + 1}\right)- {v}_{C2}\left({k + 1}\right)}\right|$
Similarly, the value function ${g}_{2}$ for the lower port is formulated as:
${g}_{2}= \left|{{i}_{\text{low }\alpha }^{* }\left({k + 1}\right)- {i}_{\text{low }\alpha }\left({k + 1}\right)}\right|+ \left|{{i}_{\text{low }\beta }^{* }\left({k + 1}\right)- {i}_{\text{low }\beta }\left({k + 1}\right)}\right|+ \\\lambda \left|{{v}_{C1}\left({k + 1}\right)- {v}_{C2}\left({k + 1}\right)}\right|$
where $\lambda$ represents a weight coefficient that determines the priority of the controlled variable in the global optimization. Utilizing time-sharing control method, only one port operates in each control cycle, The controller performs 27 optimization searches within one cycle.
C. TSC-FCS-MPC Operating Principle
The time-sharing nature of the operation, wherein simultaneous current output control for both ports is not feasible, results in a relatively low utilization rate of the DC voltage. To address this limitation, a coordinated control approach has been implemented. This approach involves the establishment of predictive models and cost functions for both the upper and lower ports. Within a single control cycle, the optimal output current for one port (upper or lower) is determined initially. Subsequently, based on the principles of time-sharing coordinated control, the optimal output current for the other port is established within the effective vector range. In the following control cycle, this process is reversed, with the previously secondary port taking priority. This alternating operation over two cycles facilitates the coordinated functioning of both ports.
The TSC-FCS-MPC methodology constructs value function ${g}_{1}$ for the upper port:
${g}_{1}= \left|{{i}_{\mathrm{{up}}\alpha }^{* }\left({k + 1}\right)- {i}_{\mathrm{{up}}\alpha }\left({k + 1}\right)}\right|+ \left|{{i}_{\mathrm{{up}}\beta }^{* }\left({k + 1}\right)- {i}_{\mathrm{{up}}\beta }\left({k + 1}\right)}\right|$
Similarly, the TSC-FCS-MPC methodology constructs the value function ${g}_{2}$ for the lower port:
${g}_{2}= \left|{{i}_{\text{low }\alpha }^{* }\left({k + 1}\right)- {i}_{\text{low }\alpha }\left({k + 1}\right)}\right|+ \left|{{i}_{\text{low }\beta }^{* }\left({k + 1}\right)- {i}_{\text{low }\beta }\left({k + 1}\right)}\right|\left({12}\right)$
1)Vector Selection Principle Based on TSC-FCS-MPC
The output three-phase voltage vectors for the upper and lower ports are defined as ${v}_{\mathrm{{up}}}= \left\lbrack {{v}_{\mathrm{U}}{v}_{\mathrm{V}}{v}_{\mathrm{W}}}\right\rbrack$ and ${v}_{\mathrm{{low}}}= \left\lbrack {{v}_{\mathrm{X}}{v}_{\mathrm{Y}}{v}_{\mathrm{Z}}}\right\rbrack$.
In contrast to traditional methods, when determining the three-phase voltage vector of one port at a given moment, the vector of the other port is not unique. The three-phase voltage vector can be selected as the optimal output state when constraints are satisfied. For instance, when the upper port outputs ${v}_{\mathrm{{up}}}= \left\lbrack \mathrm{{PON}}\right\rbrack$, the lower port can select from six states:[PON],[PNN],[OON],[ONN],[NON], and [NNN], all of which satisfy the topology’s inherent constraints. Fig. 5 illustrates the vector selection principle for ${\mathbf{v}}_{\mathrm{{up}}}= \left\lbrack \mathrm{{PON}}\right\rbrack$. When the upper port’s output state is $P$, the corresponding voltage states of the lower port can be P, O, or N. When the upper port’s voltage state is O, the lower port’s output states are limited to O and N due to topological constraints. When the upper port’s voltage state is N, the lower port’s output state is restricted to N. Based on this principle, Fig. 5 depicts the effective switching states of vlow when ${v}_{\mathrm{{up}}}= \left\lbrack \mathrm{{PON}}\right\rbrack$. The effective states are summarized as [PON],[PNN],[OON],[ONN],[NON], and [NNN]. Consequently, the effective voltage vectors for the lower port corresponding to each upper port voltage vector can be derived, as shown in Table IV.
2)TSC-FCS-MPC System
The time-sharing cooperative control operates cyclically over two control cycles. In one cycle, the upper port operates as the primary component while the lower port operates cooperatively. In the subsequent cycle, these roles are reversed.
When the upper port is the primary component, the controller performs a 27-voltage vector rolling optimization for its output current value function ${g}_{1}$. The voltage vector yielding the smallest value function is selected. After obtaining this optimal voltage vector, the controller performs a rolling optimization for the lower port’s output current value function ${g}_{2}$ based on the corresponding effective voltage vectors listed in Table III. The optimal voltage vector for the lower port is then selected. Finally, a digital signal is generated according to the switching states of the power switches corresponding to the output voltages of both ports, as outlined in Table I. The process is mirrored when the lower port operates as the primary component. After selecting the optimal voltage vector for ${g}_{2}$ through rolling optimization, the effective voltage vector for the upper port is chosen, followed by a rolling optimization to select the optimal vector for ${g}_{1}$. Fig. 6 presents a flowchart of the main operations of the TSC-FCS-MPC system when the upper port is the primary component. Fig. 7 illustrates the overall control block diagram of the system.
This method ensures prioritized operation of one port in each control cycle, with the other port operating cooperatively according to topology switch multiplexing and switch state redundancy. The alternating priority over two cycles reduces the number of optimization searches from 216 to 27-54 per control cycle, significantly enhancing computational efficiency.
IV. Simulation and Experimental Validation
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A. Simulation Results and Analysis
Simulation studies were conducted using MATLAB/Simu-link software to validate the effectiveness of the proposed TSC-FCS-MPC. The simulation parameters were set as follows: ${V}_{\mathrm{{dc}}}$ $={600}\mathrm{\;V},{T}_{\mathrm{s}}= {80\mu }\mathrm{s}$. The results of conventional FCS-MPC and TS-FCS-MPC were provided for comparison.
The operating modes of the inverter were categorized into two groups: common frequency (CF) mode and different frequency (DF) mode. In CF mode, the operating frequencies of two three-phase outputs are equal, while in DF mode, they differ.
For CF mode, the following parameters were utilized: ${i}_{\mathrm{{up}}}{}^{* }$ and ${i}_{\text{low }}$ reference currents of ${10}\mathrm{\;A}$, frequencies ${f}_{1}= {f}_{2}= {50}\mathrm{\;{Hz}}$, load resistors ${R}_{1}= {R}_{2}= {10\Omega }$, and inductors are ${L}_{1}= {L}_{2}= {15}\mathrm{{mH}}$. Fig. 8 displays the output current waveforms and their total harmonic distortion (THD) for both ports, obtained using the three strategies.
The output currents ${i}_{\mathrm{{UVW}}},{i}_{\mathrm{{XYZ}}}$ and their THDs for the upper and lower ports based on conventional FCS-MPC are presented in Fig. 8(a) and (b). The current waveforms exhibit stable sinusoidal patterns with THDs of 2.71% and 2.73%, respectively. Fig. 8(c) and (d) illustrates ${i}_{\mathrm{{UVW}}},{i}_{\mathrm{{XYZ}}}$ and their THDs for conventional TS-FCS-MPC, showing stable sinusoidal waveforms with THDs of 2.31% and 1.91%. ${i}_{\mathrm{{UVW}}},{i}_{\mathrm{{XYZ}}}$ and their THDs of the upper and lower ports based on the conventional TSC-FCS-MPC are depicted in Fig. 8(e) and (f), demonstrating stable sinusoidal waveforms with THDs of 1.92% and 1.66%. In CF mode, the THDs obtained by all three control methods comply with the national standard, which stipulates that the THD of load current in the public grid should not exceed 5%. Notably, the proposed strategy achieves higher current quality and lower THD values compared to the previous two methods.
For DF mode, the parameters were set as follows: ${i}_{\mathrm{{up}}}{}^{* }$ and ${i}_{\text{low }}{}^{* }$ reference currents of ${10}\mathrm{\;A},{f}_{1}= {50}\mathrm{\;{Hz}},{f}_{2}= {60}\mathrm{\;{Hz}}$, ${R}_{1}= {R}_{2}= {10\Omega }$, and ${L}_{1}= {L}_{2}= {15}\mathrm{{mH}}$. Fig. 9 presents the output current waveforms and their THDs for both ports, obtained using the three strategies. Fig. 10 displays the output waveforms of voltages ${v}_{\mathrm{{UVW}}}$ and ${v}_{\mathrm{{XYZ}}}$, showing sinusoidal patterns with an amplitude of ${100}\mathrm{\;V}$ for each phase.
The output wrrents ${i}_{\mathrm{{UVW}}},{i}_{\mathrm{{XYZ}}}$ and their THDs for the upper and lower ports based on the proposed TSC-FCS-MPC are shown in Fig. 9(a) and (b). The current waveforms exhibit stable sinusoidal patterns with THDs of 1.93% and 1.45%, respectively. Table V provides a comparison of current THDs obtained with the other two methods. In conclusion, the THDs obtained by all three control methods in DF mode meet the national grid standards. The proposed strategy demonstrates superior performance, achieving lower THD values and higher quality currents compared to the two previous methods.
For the time-sharing operation, the following parameters were employed: voltage ${V}_{\mathrm{{dc}}}= {600}\mathrm{\;V},{C}_{1}= {C}_{2}= {3600\mu }\mathrm{F}$, resistive inductive load ${R}_{1}= {R}_{2}= {10\Omega },{L}_{1}= {L}_{2}= {15}\mathrm{{mH}}$, and $\lambda = 2$. Fig. 11 illustrates the voltages of the capacitors. The voltages ${v}_{C1}$ and ${v}_{C2}$ on ${C}_{1}$ and ${C}_{2}$ are presented in Fig. 11(a) and (b), respectively. Both voltages stabilize at approximately ${300}\mathrm{\;V}$, with their difference maintained within $\pm {0.05}\mathrm{\;V}$, demonstrating balanced capacitor voltages.
The predictive current control method’s efficacy is highly dependent on the accuracy of inductor parameters, as evidenced by (4) and (5). The control circuit necessitates direct incorporation of inductor parameters in calculations, and its performance is contingent upon the degree of congruence between the control circuit’s inductor parameters and those of the main circuit. Discrepancies between the resistive-inductive parameters of the control and main circuits can lead to inaccurate output current values and ineffective reference current tracking. Consequently, this mismatch may result in diminished system response, reduced stability, and potential oscillations.
An analysis was conducted to evaluate the system’s control capability under parameter incompatibility. Parameter errors of ±60% were introduced, with resistance values ranging from $4 -{16\Omega }$ and inductance values from $6 -{24}\mathrm{{mH}}$. Fig. 12 presents a comparative analysis of the THD for the upper port currents using the three methods at various parameter values. Similarly, Fig. 13 illustrates the THD of the lower port currents for the three methods across different parameter values.
As depicted in FigS. 12 and 13, the output current THD for both traditional FCS-MPC and TS-FCS-MPC methods exhibits higher values at ${60}\%$ parameter error, exceeding the 5% threshold permitted by national public grid standards. In contrast, the proposed TSC-FCS-MPC method demonstrates consistently lower THD values, all below 5%, thereby adhering to the national standards for permissible load current THD in public grids. This method maintains superior overall current quality, ensuring that system stability remains unaffected by parameter mismatches.
B. Experimental Validation
To substantiate the viability of the proposed topology and strategy, a hardware-in-the-loop testing platform was constructed based on the experimental setup illustrated in Fig. 14. The main circuit was implemented in the TyphoonHIL 402 semi-physical platform, with pulse signals generated by an HDSP-DF28335P real-time controller. Voltage and current harmonic distortion rates were analyzed using a HIOKI power quality analyzer PQ3198. The experimental parameters were configured to match those used in the simulation.
1) In ${CF}$ Mode
Fig. 15 presents the three-phase output current waveforms for the upper and lower ports, comparing the three strategies: conventional FCS-MPC, TS-FCS-MPC, and TSC-FCS-MPC in CF mode. The corresponding THD values for these currents are displayed in Fig. 16.
The experimental results depicted in Figs. 15 and 16 demonstrate that the output three-phase currents at both the upper and lower ports exhibit stable sinusoidal waveforms in CF mode for all three control strategies. The THD values of these currents are consistently below 5%. Notably, the proposed control strategy yields superior current quality compared to the two preceding methods, aligning with the simulation outcomes.
2) In ${DF}$ Mode
Fig. 17 illustrates the three-phase output current waveforms for the upper and lower ports, comparing the conventional FCS-MPC, TS-FCS-MPC, and TSC-FCS-MPC strategies in DF mode. The corresponding THD values for these currents are presented in Fig. 18.
As evidenced by Figs. 17 and 18, the proposed control strategy demonstrates overall superior performance in DF mode compared to both the conventional FCS-MPC and time-sharing control methods. These findings corroborate the simulation results.
3) Dynamic Performance
To further assess the dynamic performance, a reference current frequency of ${f}_{1}= {f}_{2}= {50}\mathrm{\;{Hz}}$ was applied to ${i}_{\mathrm{{up}}}{}^{* }$ and ${i}_{\mathrm{{low}}}{}^{* }$ in CF mode. Subsequently, the amplitude of ${i}_{\mathrm{{up}}}{}^{* }$ was abruptly altered from ${10}\mathrm{\;A}$ to ${15}\mathrm{\;A}$. Fig. 19 illustrates the dynamic responses of the three control strategies under these conditions.
To validate the efficacy of the proposed control method in reducing computational burden, the predicted operation times of the three control methods were compared, as shown in Fig. 20. The conventional FCS-MPC strategy requires a prediction operation time of ${62.88\mu }\mathrm{s}$, constituting ${78.6}\%$ of the control cycle time. The TS-FCS-MPC strategy necessitates ${26.96\mu }\mathrm{s}$, accounting for 33.7% of the control cycle time. The TSC-FCS-MPC strategy requires ${32.72\mu }\mathrm{s}$, representing ${40.9}\%$ of the control cycle time. This represents a 48% reduction in computing time compared to the conventional FCS-MPC. Although the number of optimization searches per control cycle is increased compared to the TS-FCS-MPC, resulting in a ${5.76\mu }\mathrm{s}$ increase in computing time, these findings align with the theoretical analysis.
In conclusion, the proposed TSC-FCS-MPC strategy demonstrates superior output current waveform quality, enhanced dynamic stability, and reduced prediction arithmetic compared to the traditional FCS-MPC. These improvements result in enhanced system response speed and stability. Furthermore, when compared to the TS-FCS-MPC, the TSC-FCS-MPC achieves coordinated operation of the upper and lower output ports, thereby enhancing the overall output performance of both ports.
V. Conclusion
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A novel DP-TLI topology has been proposed in this paper, which simplifies the structure through switch multiplexing, thereby reducing system costs. To complement this topology, a TSC-FCS-MPC strategy has been introduced. This strategy incorporates coordinated control on top of time-sharing control, treating two control cycles as a single loop. Consequently, the coordinated operation of both ports is enabled, fully utilizing the redundancy in switch states offered by the device multiplexing of the proposed topology. This approach significantly enhances the overall output performance of the inverter. Furthermore, the prediction computation has been substantially reduced from the traditional exhaustive optimization method of 216 iterations to a mere 27 to 54 iterations. This reduction markedly improves the system’s operational efficiency and response speed. The effectiveness of the proposed topology and control strategy has been rigorously validated through both simulation and experimental results.
Funding
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  • Basic Research Program of Jiangsu Education Department(KYCX23_2913)
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Year 2024 volume 9 Issue 4
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Cite this Article
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Article Info
doi: 10.24295/CPSSTPEA.2024.00027
  • Receive Date：2024-07-07
  • Online Date：2025-07-05
  • Published：2024-12-10
Article Data
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History
  • Received：2024-07-07
  • Revised：2024-10-29
  • Accepted：2024-11-21
Funding
Basic Research Program of Jiangsu Education Department(KYCX23_2913)
Affiliations
    Jiangsu Normal University College of Electrical Engineering and Automation Xuzhou 221116 China

Corresponding:

Fei Wang.
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表12种不同金属材料的力学参数
科
Family		 属数
Number of
genus		 种数
Number of
species		 占总种数比例
Percentage of
total species (%)		 属
Genus		 种数
Number of
species		 占总种数比例
Percentage of total
species (%)
鹅膏菌科Amanitaceae 2 11 5.26 鹅膏菌属 Amanita 10 4.78
小菇科 Mycenaceae 2 12 5.74 丝盖伞属 Inocybe 5 2.39
多孔菌科 Polyporaceae 8 14 6.70 蜡蘑属 Laccaria 5 2.39
红菇科 Russulaceae 3 23 11.00 小皮伞属 Marasmius 6 2.87
小菇属 Mycena 11 5.26
光柄菇属 Pluteus 5 2.39
红菇属 Russula 17 8.13
栓菌属 Trametes 5 2.39
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