Twelve-Step Voltage Source Inverter: A Three-Phase Six-Levels Inverter Using Planar Transformers

Twelve-Step Voltage Source Inverter: A Three-Phase Six-Levels Inverter Using Planar Transformers

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Haitham KANAKRI, Euzeli Cipriano DOS SANTOS JR., Maher RIZKALLA

CPSS Transactions on Power Electronics and Applications | 2024, 9(3) : 263 - 273

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CPSS Transactions on Power Electronics and Applications | 2024, 9(3): 263-273

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Twelve-Step Voltage Source Inverter: A Three-Phase Six-Levels Inverter Using Planar Transformers

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Haitham KANAKRI, Euzeli Cipriano DOS SANTOS JR., Maher RIZKALLA

Affiliations

Purdue University Purdue School of Engineering and Technology Indianapolis 46202-5143 United States

Haitham M. Kanakri was born in Irbid, Jordan, in 1989. He received the B.S. degree in electrical engineering from the University of Jordan, Amman, Jordan, in 2013, the M.S. degree in power electronics in 2015 from Texas A&M University, College Station, Texas, USA, and the M.S. degree in power systems from Kansas State University, Manhattan, Kansas in 2019. In 2015 he was a student intern with Schneider Electric company, Houston, Tx, USA, where he worked on ecostruxure buildings and control. He is currently a research assistant with Purdue School of Engineering and Technology Indianapolis campus where he is pursuing his Ph.D. degree in electrical and computer engineering. His research interests include power electronics, planar magnetic design, high-power density converters, motor drive systems, capacitor-less converters, active output filtering, and LLC resonant converters.

Euzeli Cipriano dos Santos, Jr. was born in Picui, Brazil, in 1979. He received the B.S., M.S., and Ph.D. degrees in electrical engineering from the Federal University of Campina Grande, Campina Grande, Brazil, in 2004, 2005, and 2007, respectively. From 2006 to 2007, he was with the Electric Machines and Power Electronics Laboratory, Texas A&M University, College Station, TX, USA, as a Visiting Scholar. From August 2006 to March 2009, he was a Professor with the Federal Center of Technological Education of Paraiba, Brazil. From December 2010 to March 2011, he was a Visiting Professor with the University of Siegen, Germany, sponsored by DAAD/CAPES. From 2009 to 2012, he was with the Department of Electrical Engineering, Federal University of Campina Grande, as a Professor of electrical engineering. From 2012 to 2024, he was with IUPUI. He has been with Purdue University since 2024 where he is currently an Associate Professor. His research interests include power electronics, renewable energy systems, and electrical drives.

Maher Rizkalla received his Ph.D. degree in electrical engineering from Case Western Reserve University, Cleveland, OH, USA, in 1985. From January 1985 to August 1986, he was a Research Scientist at Argonne National Laboratory, Lemont, Illinois, USA, while he was a Visiting Assistance Professor, Department of Electrical Engineering at Purdue University Calment, Hammond, Indiana, USA. He joined the Department of Electrical and Computer Engineering, Indiana-University Purdue University Indianapolis (IUPUI) in August 1986. He became a Professor in 1996, and Associate Chair from 2005 to 2024. Currently, he is a Professor, Department of Electrical and Computer Engineering at Purdue University. He has authored and coauthored more than 250 conference and journal papers since he joined the Department of Electrical and Computer Engineering at IUPUI. He is the recipient of three NSF grants and two others from the Department of Education. He is also a Co-PI on several industrial grants. His research interests include solid state electronics, superconducting, semiconducting, and nanotechnology devices, VLSI design, and electromagnetics as applied to health sciences. He is a Professional Engineer registered in the state of Indiana.

Published: 2024-09-10 doi: 10.24295/CPSSTPEA.2024.00011

Outline

Abstract

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Multilevel inverters (MLIs) are becoming increasingly popular in highspeed motor drive systems for modern electric aircraft applications. However, two significant limitations are associated with current MLIs technology: (1) the high switching losses due to the high carrier switching frequency and (2) the complex modulation schemes required to maximize the DC source utilization. Consequently, the development of new topologies to mitigate these limitations is imperative for the rapid advancement of future electric aircraft systems. This paper introduces a sixlevel twelvestep inverter (TSI) that utilizes twelve switches and three planar highfrequency transformers. Implementing the proposed configuration ensures maximum DC source utilization, with a peak phase voltage of 5Vdc / 3. The proposed solution presents less semiconductor losses than the conventional MLIs, surpassing conventional MLIs, associated with neutral point clamped (NPC), flying capacitor (FC), and cascaded Hbridge (CHB). Experimental results demonstrate the TSI's operation under static and dynamic conditions and its capability to function in three different modes: threestep, sixstep, and twelvestep operations. The paper also offers a comprehensive design of the proposed planar transformer, supported by theoretical analysis, finite element analysis (FEA), and experimental validation.

Key words

Finite element analysis (FEA) / multilevel inverters / planar transform design / six-level output voltage / three-phase inverter / twelve-step inverter

Cite this Article

Haitham KANAKRI, Euzeli Cipriano DOS SANTOS JR., Maher RIZKALLA. Twelve-Step Voltage Source Inverter: A Three-Phase Six-Levels Inverter Using Planar Transformers[J]. CPSS Transactions on Power Electronics and Applications, 2024 , 9 (3) : 263 -273 . DOI: 10.24295/CPSSTPEA.2024.00011

Full Text

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NOMENCLATURE

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${A}_{\mathrm{c}}$	Transformer’s core cross sectional area $\left({\mathrm{{cm}}}^{2}\right)$.
${A}_{\mathrm{t}}$	PCB copper trace cross-sectional area in $\left({\mathrm{{mils}}}^{2}\right)$.
${A}_{\mathrm{t},\left\lbrack {\mathrm{{cm}}}^{2}\right\rbrack }$	PCB copper trace cross-sectional area in $\left({\mathrm{{cm}}}^{2}\right)$.
${A}_{\mathrm{p}}$	Area product $\left({\mathrm{{cm}}}^{4}\right)$.
${B}_{\mathrm{m}}$	Maximum flux density (T).
$f$	Operating frequency in (Hz).
${i}_{1}$	Phase-u load current.
${i}_{2}$	Phase-v load current.
${i}_{3}$	Phase-w load current.
J	Current density in $\left({\mathrm{A}/{\mathrm{{cm}}}^{2}}\right)$.
k	Constant related to conductor current density specified by IPC-221A standard for outer and inner PCB layers.
${K}_{\mathrm{f}}\;$	Waveform coefficient.
${K}_{\mathrm{u}}\;$	Transformer window utilization factor.
$n$	Transformer turns ratio.
${P}_{0}$	Transformer output power.
${P}_{\mathrm{t}}\;$	Transformer total handling power.
${S}_{\mathrm{x}}$	Switch X, where $x =\{ 1, a,2, b,3, c\}$.
${\bar{S}}_{\mathrm{x}}$	Complementary of switch X.
TSI	Twelve-step inverter.
${V}_{\mathrm{{dc}}}$	DC input voltage.
${V}_{\text{un }}$	Phase u to neutral n voltage.
${V}_{\text{vn }}$	Phase $\mathrm{v}$ to neutral $\mathrm{n}$ voltage.
${V}_{\text{wn }}$	Phase w to neutral $\mathrm{n}$ voltage.
${v}_{ac}\;$	The primary voltage of transformer-1.
${v}_{ba}\;$	The primary voltage of transformer-2.
${v}_{cb}\;$	The primary voltage of transformer-3.
${v}_{ac}^{\prime }\;$	The secondary voltage of transformer-1.
${v}_{ba}^{\prime }\;$	The secondary voltage of transformer-2.
${v}_{cb}^{\prime }\;$	The secondary voltage of transformer-3.
${W}_{\mathrm{a}}\;$	Transformer core window area $\left({\mathrm{{cm}}}^{2}\right)$.
$\eta$	Transformer efficiency (%).
${\Delta T}\;$	Temperature rise $\left({{}^{\circ }\mathrm{C}}\right)$.
$\Phi$	Magnetic flux (Weber).

I. INTRODUCTION

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THE growing interest in DC-AC converters for applications that demand minimal harmonic distortion has prompted engineers to operate at higher switching frequencies [1]. However, the selection of an operating frequency is notably constrained by the specific type of switching device employed within a given application, such as MOSFETs or IGBTs. Indeed, increased switching frequencies can lead to higher losses, consequently placing restrictions on the overall system performance. Multilevel PWM inverters (MLI) are commonly employed in applications requiring minimal harmonic distortion, including motor drive systems and grid-tie inverters [2]. Common topologies include neutral-point clamped (NPC)[3], flying capacitor (FC)[4]-[6] and cascaded multi-cells (CHB) configurations with separate DC sources [1],[4]. While PWM inverters can produce an output current that closely resembles a sine wave with minimal harmonic distortion [7],[8], they come with some drawbacks. These include complex strategies for an optimized PWM and converter design in order to reduce the switching losses [9],[10], increased weight and volume for heat sink requirements [11], acoustic noise [12], and issues related to electromagnetic interference (EMI)[12],[13]. Additionally, PWM inverters suffer from the use of multiple DC-link capacitors, particularly in the case of the NPC topology. When only one DC source is available, without appropriate modulation and control strategies, there wouldn’t be assurance that the capacitor voltages will reach the desired levels, potentially leading to asymmetric output voltages [2]. Consequently, the use of feedback controllers with specific PWM approaches becomes necessary, thereby increasing the complexity of the system [2].

Due to the substantial demand for high-power inverters with medium voltage levels, there has been rapid evolution in the need for new MLIs with reduced switching losses [14]. MLIs can be categorized into two types: 1) carrier-based variable duty cycle PWM inverters, such as the NPC, FC, and CHB inverters [1], and 2) fixed duty cycle PWM inverters, such as the six-step inverter [15]. Although the six-step inverter may introduce higher low-frequency distortions, its low operating frequency becomes appealing when the size and volume of the controlled voltage source become critical factors [15]. For instance, in aerospace applications, the electrically powered high-lift system that uses high-speed permanent magnet motor of 60000 RPM connected to the air compressor and integrated into the aircraft wings structure [16]-[18]. Moreover, these applications prioritize high power density, with typical power/ mass ratios reaching 4kW/kg [19].

The six-step inverter refers to a three-phase DC-AC converter built using six IGBTs operating with a 50% duty cycle, does not have high-frequency variable duty-cycle PWM gate signals. The authors in [15] proposed a control scheme for the six-step operation of permanent magnet synchronous machine (PMSM) with current control, ensuring it’s enhanced dynamic performance. Similarly, the authors in [20] utilized squarewave inverter operation for a three-phase motor drive system, in order to increase voltage utilization and achieve higher efficiency compared to that of the PWM operation [21]. The authors of [22] showed that the six-step operation can achieve a higher power density and lower switching frequency compared to PWM operation. In [13], the authors proposed an 18-step inverter, comprising 12 IGBTs, 36 power diodes, and three DC link capacitors to achieve an output voltage of seven levels. However, the high number of components and the adoption of a modified PWM scheme to further decrease the low-order harmonics in the output current elevate the complexity of control. Although this topology offers the advantage of a single DC source, it still uses multiple DC link capacitors, leading to increased system costs and size.

Transformer based multi-level inverters (Tr-MLI)[23] are commonly utilized to increase voltage levels for highpower and high-voltage applications. They offer capacitor free and diode-free topologies, facilitating voltage boosting with straight forward control [24]. The multilevel cascaded H-bridge inverter, proposed in [25] for medium-voltage applications, improves the system efficiency and reduces component count. Tr-MLIs are preferred in motor drive applications due to their use of a single DC source, mitigating the power balance issues inherent in conventional MLIs [26]. The emergence of planar magnetic technology has enabled the incorporation of multiple transformers in converter structures without compromising overall converter size and efficiency [27]. Indeed, planar magnetic technology shows promise in meeting the escalating demands for high-power density and low-profile converters [28]. Various applications, such as modern electric aircraft [29], automotive industry such as electric vehicles, servers, aerospace, and military applications [28], integrate planar transformers in their structures to achieve high-power density and streamlined profile products. A twelve-step three-phase six-level inverter (TSI) published by the authors of this work is introduced in [30]. Fig. 1 illustrates the proposed topology. Notably, the proposed configuration offers several key features:(1) complete elimination of the DC link capacitors, resolving voltage balance issues,(2) utilization of a single DC source,(3) reducing inverter semiconductor losses,(4) simplifying switching and control algorithm, and (5) reducing the overall size of the inverter due to the use of high-frequency planar transformers. Additionally, the proposed topology provides the highest number of levels at the output voltage per number of DC sources $\left({L/{S}_{\mathrm{{dc}}}= 6/1}\right)$ among all other MLI topologies. It stands as a candidate for high-speed motor drive systems, particularly with permanent magnet synchronous machines (PMSM) when operating at very high frequencies, where the use of PWM MLIs is constrained by high-switching losses.

After this introduction, Section II highlights the novelty and applications of the proposed topology, Section III presents the modeling and operating principles, Section IV discusses the design of the proposed planar transformers, Section V provides detailed simulations and experimental results, Section VI presents the efficiency analysis and comparison with the current MLIs topologies, and finally, Section VII concludes the proposed work.

II. Novelty and Applications of the Proposed TOPOLOGY

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While transformer-based inverters are a well-established technology [31], the proposed configuration stands out for its ability to operate over a wide range of fundamental frequencies. The innovative design of the high-frequency planar transformer enables the operation at exceptionally high efficiency. This transformer design incorporates a balanced winding configuration, winding with simple construction, and reduces the construction cost. Applications such as electrically powered high-lift systems in aircrafts are particularly suitable for the proposed topology. Electric aircraft utilizes high-speed motors to drive aircraft compressors, as depicted in Fig. 2(a)[17],[18]. High-speed permanent magnet synchronous machines (PMSM) are typically integrated into the aircraft wings and compressor assemblies, operating at high fundamental frequencies exceeding 60000 RPM [17],[18]. The use of traditional MLIs for such applications is limited due to high switching losses. The number of switching components for a typical MLI topology increases with the number of levels, consequently increasing the size and cost of the drive system. This limitation is particularly critical for electric aircraft applications, as the power electronics drive system must be integrated into the aircraft wings, as shown in Fig. 2(b). Some key features of the proposed configuration include uniform voltage levels at the output and the equivalence of phase and line voltages in terms of the number of levels. Moreover, the phase voltages surpass the DC-link voltage, which allows higher current and consequently increases motor torque.

III. Modeling and Operation of the Proposed TWELVE-STEP INVERTER (TSI)

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The inverter, depicted in Fig. 3(a), is comprised of twelve insulated gate bipolar transistors (IGBTs), twelve freewheeling diodes, three high-frequency planar transformers, and a single DC-link voltage source. Notably, the design does not necessitate any additional voltage divider capacitors. The DC-link capacitors shown in Fig. 3(a) are utilized exclusively for modeling purposes and are not required for the system’s operation. The primary side of the transformers is connected in delta arrangement, while the secondary side is linked to the Y-load and inverter legs. The innovative topology produces six distinctive levels at the output voltage, namely, $5{V}_{\mathrm{{dc}}}/3$, $4{V}_{\mathrm{{dc}}}/3,{V}_{\mathrm{{dc}}}/3,- {V}_{\mathrm{{dc}}}/3,- 4{V}_{\mathrm{{dc}}}/3$, and $- 5{V}_{\mathrm{{dc}}}/3$, resulting in a comprehensive twelve-step waveform, as illustrated in Fig. 3(d). Remarkably, the peak-to-peak amplitude of the output phase voltage is ${3.33}{V}_{\mathrm{{dc}}}$, a significant increase when compared to the conventional six-step inverter with a peak-to-peak phase voltage of ${1.33}{V}_{\mathrm{{dc}}}$. For further clarity, the equivalent circuit of the TSI topology is illustrated in Fig. 3(b). The analysis of the six-level load phase voltage ${v}_{\mathrm{{un}}}$ based on the proposed switching pattern is presented in Table I and Table II. Table II shows the switching pattern to obtain the six-level output phase voltage. Table I also details the switching pattern of the twelve-step action used to generate the six-level waveform. The load phase voltages are 120° apart. The step size of each twelve-step action is 30°, for example, step-1 is located between 0° and 30°, step-2 is located between 30° and 60° and so on till step-12 which is located between 330° and 360°. The resultant pole voltages applied to the load are derived as follows:

(1)

${v}_{10}= {v}_{ac}^{\prime }+ {v}_{\text{un }}+ {v}_{n0}$

(2)

${v}_{20}= {v}_{ba}^{\prime }+ {v}_{\mathrm{{vn}}}+ {v}_{n0}$

(3)

${v}_{30}= {v}_{cb}^{\prime }+ {v}_{\mathrm{{wn}}}+ {v}_{n0}$

where the voltages ${v}_{ac}^{\prime },{v}_{ba}^{\prime },{v}_{cb}^{\prime }$ are the secondary voltages of the transformers connected to phase u, v, and w, respectively. If the number of turns of each transformer is $n,\left( 1\right)- \left( 3\right)$ become:

(4)

${v}_{10}= n{v}_{ac}+ {v}_{\mathrm{{un}}}+ {v}_{n0}$

(5)

${v}_{20}= n{v}_{ba}+ {v}_{\mathrm{{vn}}}+ {v}_{n0}$

(6)

${v}_{30}= n{v}_{cb}+ {v}_{\mathrm{{wn}}}+ {v}_{n0}$

where ${v}_{ac}= {v}_{a0}- {v}_{c0},{v}_{ba}= {v}_{b0}- {v}_{a0},{v}_{cb}= {v}_{c0}- {v}_{b0}$. Notice that the load phase voltages can be written in terms of the pole voltages ${v}_{10},{v}_{a0},{v}_{20},{v}_{b0},{v}_{30}$, and ${v}_{c0}$. Then the phase load voltages become:

(7)

${v}_{\mathrm{{un}}}= {v}_{10}- n{v}_{ac}- {v}_{n0}$

(8)

${v}_{\mathrm{{vn}}}= {v}_{20}- n{v}_{ba}- {v}_{n0}$

(9)

${v}_{\mathrm{{wn}}}= {v}_{30}- n{v}_{cb}- {v}_{n0}$

For a three-phase balanced system and assuming, $n = 1$,

(10)

${v}_{n0}= \frac{1}{3}\left({{v}_{10}+ {v}_{20}+ {v}_{30}}\right)$

Substituting (10) in (7)-(9), it yields:

(11)

${v}_{\mathrm{{un}}}= \frac{2}{3}{v}_{10}- {v}_{a0}- \frac{1}{3}{v}_{20}- \frac{1}{3}{v}_{30}+ {v}_{c0}$

(12)

${v}_{\mathrm{{vn}}}= \frac{2}{3}{v}_{20}- {v}_{b0}- \frac{1}{3}{v}_{30}- \frac{1}{3}{v}_{10}+ {v}_{a0}$

(13)

${v}_{\mathrm{{wn}}}= \frac{2}{3}{v}_{30}- {v}_{c0}- \frac{1}{3}{v}_{10}- \frac{1}{3}{v}_{20}+ {v}_{b0}$

Since each pole voltage is defined by the state of the switches ${S}_{j}\left({\text{with}j = 1, a,2, b,3, c}\right)$ following ${v}_{j0}= \left({2{S}_{j}- 1}\right)\left({V}_{\mathrm{{dc}}}\right.$ / 2), the connection of the high-frequency transformers allows each pole voltage seen by the three-phase load $\left({{v}_{\mathrm{u}0},{v}_{\mathrm{v}0},{v}_{\mathrm{w}0}}\right)$ to be:

(14)

${v}_{\mathrm{u}0}= {v}_{10}+ {v}_{c0}- {v}_{a0}$

(15)

${v}_{\mathrm{v}0}= {v}_{20}+ {v}_{a0}- {v}_{b0}$

(16)

${v}_{\mathrm{w}0}= {v}_{30}+ {v}_{b0}- {v}_{c0}$

It is possible to select the gate signals for each phase so that the voltages ${v}_{\mathrm{u}0},{v}_{\mathrm{v}0},{v}_{\mathrm{w}0}$ have four levels as presented schematically in Fig. 3(c). Finally, the line voltages can be given in terms of the pole voltages as follows in (17)-(19):

(17)

${v}_{\mathrm{{uv}}}= {v}_{10}- {v}_{20}+ {v}_{b0}+ {v}_{c0}- 2{v}_{a0}$

(18)

${v}_{\mathrm{{vw}}}= {v}_{20}- {v}_{30}+ {v}_{a0}+ {v}_{c0}- 2{v}_{b0}$

(19)

${v}_{\mathrm{{wu}}}= {v}_{30}- {v}_{10}+ {v}_{a0}+ {v}_{b0}- 2{v}_{c0}$

IV. Planar Transformer Design

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In contrast to the traditional transformers with large core heights, planar transformers offer a compact design solution, as highlighted in [32]. Their integration into power electronics inverters and the power conversion process is attributed to their high-power density, superior performance, and costeffectiveness. Advancements in planar magnetics technology have been facilitated by the use of low-profile ferrite cores, enabling operation at high frequencies, often in the range of several tens of kilohertz [33].

The increased adoption of planar transformers in power electronics inverters is not solely due to the core height and ferrite material; factors such as cost-effectiveness, mechanical robustness, and improved thermal responses contribute significantly to their popularity [33]. The precise construction of planar transformers, with each primary and secondary turn positioned meticulously within the core according to PCB layouts, facilitates better control over leakage inductance. This has rendered planar transformers particularly valuable in various converter families, including resonant LLC converters [32]. Standardizing insulating materials ensures consistent capacitance between layers, leading to enhanced predictability in the design and transformer performance [32],[34]. The typical structure of an EE-core planar transformer, as shown in Fig. 4(a), comprises the EE-core, primary and secondary windings, and insulation layers. Designing a planar transformer necessitates adherence to specific design constraints. Notably, these constraints include satisfying the output power requirements, meeting voltage regulation limits, and ensuring minimum efficiency and maximum permissible temperature rise [32]. Conventionally employed methodologies for designing conventional transformers, such as the area product ${A}_{\mathrm{p}}$, which involves the product of the core window area ${W}_{\mathrm{a}}$ and the core cross-sectional area ${A}_{\mathrm{c}}$ (as depicted in Fig. 4(b)), and the core geometry ${K}_{\mathrm{g}}$ coefficient, are also applicable to planar transformer design. Both methodologies influence several critical design parameters, including power handling capacity, regulation capability, transformer size, weight, surface area, current density, and geometry [32]. In this study, the authors have adopted the area product methodology for its analytical design, primarily due to the availability of specific parameters in the core manufacturer’s data sheet. While both methodologies yield similar design outcomes, the area product is preferred for its suitability in analytical design processes. Subsequent to the analytical analysis, the design is further validated using finite element analysis solver in Ansys Maxwell to verify its performance in the proposed twelve-step inverter. The design parameters for the planar transformer in the twelve-step inverter are summarized in Table III. The design process starts with the computation of the total power handling capability of the transformer, as outlined in (20),(21), and (22). Adhering to the IPC-221A standard of printed circuit boards, the minimum width and thickness of conductors must be determined based on the current-carrying capacity and the maximum permissible conductor temperature.

(20)

${P}_{\text{in }}= \frac{{P}_{\mathrm{o}}}{\eta }= \frac{{3.5}\times {10}^{3}}{0.98}= {3.57}\mathrm{\;{kW}}$

(21)

${P}_{\mathrm{t}}= {P}_{\mathrm{o}}\left({\frac{1}{\eta }+ 1}\right)$

(22)

${P}_{\mathrm{t}}= {3.5}\times {10}^{3}\times \left({\frac{1}{0.98}+ 1}\right)= {7.07}\mathrm{\;{kW}}$

(23)

$ I ={k\Delta }{T}^{0.024}{A}_{\mathrm{t}}^{0.725}$

where $I$ in is the current in amperes, ${A}_{\mathrm{t}}$ is the cross sectional area of the copper trace in mils ${}^{2},{\Delta T}$ is the temperature rise in ${}^{\circ }\mathrm{C}$ and $k$ is a constant determined by the type of PCB layer: $k ={0.048}$ for outer layers and $k ={0.024}$ for inner layers. The conductor’s permissible temperature rise is defined as the difference between the maximum safe operating temperature of the printed board laminate material and maximum temperature of the thermal environment to which the printed board will be subjected [35]. In our design, we considered inner layers with maximum temperature rise of ${10}^{\circ }\mathrm{C}$. Therefore, the minimum cross-sectional area of copper trace is equal to: ${267.3}{\mathrm{{mils}}}^{2}$ or ${0.0017}{\mathrm{\;{cm}}}^{2}$. The current density $J$ of the conductor defined as the total current divided by the cross sectional area of the conductor is given as:

(24)

$ J =\frac{I}{{A}_{\mathrm{t}\left\lbrack {\mathrm{{cm}}}^{2}\right\rbrack }}$

(25)

$ J =\frac{1.5}{0.0017}= {857.7}\mathrm{\;A}/{\mathrm{{cm}}}^{2}$

Next, the area product ${A}_{\mathrm{p}}$ is calculated, which is the power handling capability of the core for the transformer:

(26)

${A}_{\mathrm{p}}= \frac{{P}_{\mathrm{t}}\times {10}^{4}}{{K}_{\mathrm{f}}{K}_{\mathrm{u}}f{A}_{\mathrm{c}}{B}_{ac}J}$

where ${K}_{\mathrm{f}}$ is the waveform coefficient.

${K}_{\mathrm{f}}= \left\{\begin{array}{l}{4.0}: \text{ for a square-wave }\\{4.44}: \text{ for a sine wave }\end{array}\right.$

The coefficient of 4.0 is well explained by Faraday’s law where:

(27)

$ v = n\frac{\mathrm{d}\Phi }{\mathrm{d}t}$

Since $\Phi = B{A}_{c}$,(27) can be rewritten as:

(28)

$ v = n{A}_{\mathrm{c}}\frac{\mathrm{d}B\left( t\right)}{\mathrm{d}t}$

The slope of the $B\left( t\right)$ curve shown in Fig. 4(c) equals to:

(29)

$\frac{\mathrm{d}B\left( t\right)}{\mathrm{d}t}= {4.0}{B}_{\max }f $

Consequently,(28) can be simplified to:

(30)

${V}_{\text{average }}= {4.0}{B}_{\max }N{A}_{\mathrm{c}}f $

The same principle applies for the sine-wave type of voltage excitation and the factor 4.44 can be justified in the same manner. The core window utilization factor, ${K}_{\mathrm{u}}$, is assumed to be 0.128 or 12.8% for the cost and weight consideration. The cross-sectional area of the core ${A}_{\mathrm{c}}= {3.08}{\mathrm{\;{cm}}}^{2}$ is selected based on the relationship between the current density and area product provided in [32]. Combining (22),(26) and the design information given in Table III, the area product is:

(31)

${A}_{\mathrm{p}}= \frac{{3.5}\times {10}^{3}\times {10}^{4}}{{4.2}\times {0.128}\times {5000}\times {3.08}\times {0.3}\times {857.7}}= {17.25}{\mathrm{\;{cm}}}^{4}$

The commercially available core that is close to the calculated area product was found to be E58/11/38 as given by the Ferroxcube company. The material is selected to be 3F4 that satisfies our maximum flux density of 0.33T. The shape of this core is shown in Fig. 4(d) with the dimensions indicated in the same figure.

The area product for the selected core ${A}_{\mathrm{p}}$ which is the power handling capability of the transformer core can be calculated as follows:

(32)

${A}_{\mathrm{p}}= {W}_{\mathrm{a}}{A}_{\mathrm{c}}= {16.80}{\mathrm{\;{cm}}}^{2}$

where ${W}_{a}= {5.447}{\mathrm{\;{cm}}}^{2}$ is the window area, ${A}_{\mathrm{c}}= {3.08}{\mathrm{\;{cm}}}^{2}$ is the cross-sectional area of the EE-core and indicated in Fig. 4(b). Next, the number of primary turns can be calculated using Faraday’s law. Given that the primary voltage ${V}_{\mathrm{p}}= {130}\mathrm{\;V}$, the number of turns can be given by:

(33)

${N}_{\mathrm{p}}= \frac{{V}_{\mathrm{p}}\times {10}^{4}}{{K}_{\mathrm{f}}{B}_{\mathrm{m}}f{A}_{\mathrm{c}}}= {70}$

The proposed design is first created using Ansys PEMag, then imported to Ansys Maxwell for electromagnetic simulations. The proposed transformer 3D geometry is shown in Fig. 4(e). An equivalent circuit model is developed based on the work published in [34], and the finite element analysis is used to extract the parameters of the equivalent circuit model. The stray capacitances are found to be: intra capacitance ${C}_{11}$ $={793.48}\mathrm{{pF}}$, and both inter capacitance ${C}_{12}= {54.86}\mathrm{{pF}},{C}_{o12}=$ ${1.64}\mathrm{{nF}}$. A complete summary of the transformer parameters including the DC resistance, AC resistance, magnetizing inductance and the leakage inductance are summarized in Table IV. Partially interleaved structure is adopted in this design to allow for balance design between the current carrying capacity and minimizing the stray capacitance values [28]. The PPSSPPSSPPSSPPSSPPSS layers arrangement is adopted. The double layer PCBs are used, each PCB represents PP or SS arrangement, the top layer is connected in series with the bottom layer to increase the number of winding, and each PCB of the same type are connected in parallel to rest of PCBs. The detailed connections and layers arrangements are shown in Fig. 4(g). The transformer layers are built professionally using 56.7g of copper and (≈0.07mm) thickness, the FR4 thickness is selected to be (≈0.7874mm) to allow more number of layers (increase the utilization factor) without compromising the stray capacitance. A Kapton tape layers is used to insulate the PCBs. The thickness of this insulation is ≈0.1mm. The tented via is used to provide connections between the top and bottom layers and multiple pads are added on the edges of each PCB to provide alignments and mechanical integrity of the transformer. The three identical transformers are built and shown in Fig. 5(b).

V. Simulation and Experimental Results

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This section provides a comprehensive account of the simulation and experimental validation of the twelve-step inverter featuring the proposed EE planar transformer. Operating at an input voltage of 25V and a load resistor of 66Ω, the setup operates at a frequency of 5 kHz. The Microchip dspic33ck256mp508 microcontroller is responsible for generating the necessary digital gate signals, ensuring precise phase shifts between the legs. The construction of the inverter utilizes the BSM75GB60DLC IGBT module. The complete setup configuration is visually depicted in Fig. 5(a), emphasizing the arrangement of the three planar transformers illustrated in Fig. 5(b). Using Ansys Maxwell and Ansys Twin-Builder under identical test conditions, the simulation yielded conclusive results. As depicted in Fig. 5(c), the TSI main voltages for phase $\mathrm{u}$ are showcased, specifically highlighting ${v}_{10}$ at the top, ${v}_{ac}$ in the middle, and ${v}_{\mathrm{u}0}$ at the bottom. The corresponding experimental verification results are presented in Fig. 5(f), featuring ${v}_{10}$ at the top, ${v}_{ac}$ in the middle, and ${v}_{\mathrm{u}0}$ at the bottom. Furthermore, Fig. 5(d) exhibits the phase voltages $\left({v}_{\mathrm{{un}}}\right.$ on top, ${v}_{\mathrm{{vn}}}$ in the middle, and ${v}_{\mathrm{{wn}}}$ at the bottom), with the corresponding experimental validation displayed in Fig. 5(g). Providing a comprehensive representation of the phase and DC currents, Fig. 5(e) and Fig. 5(h) present a visual depiction from top to bottom, including ${i}_{\mathrm{{un}}}$ (first), ${i}_{\mathrm{{vn}}}$ (second), ${i}_{\mathrm{{wn}}}$ (third), and ${i}_{\mathrm{{dc}}}$ (fourth), all validated through simulation and experimental analysis. To evaluate the effectiveness of the proposed topology under dynamic conditions, replicating a startup ramp on the voltage to reduce the inrush current of PMSM, the inverter was tested to transition between three-steps, six-steps, and twelve-steps operation modes. As depicted in Fig. 6(a), the output phase voltage is precisely controlled to ensure three, four, and six voltage levels. The transition between the various operational modes is experimentally verified, as demonstrated in Fig. 6(b). This precise control is achieved by adjusting the phase shift applied to each inverter leg as illustrated in Fig. 7. Through the implementation of the proposed method, the configuration effectively demonstrates its ability to drive Permanent Magnet Synchronous Motors (PMSM) with instantaneous current control. Additionally, this method can be effectively utilized to establish constant $\mathrm{V}/\mathrm{{Hz}}$ speed control of PMSM [37].

VI. EFFICIENCY ANALYSIS AND COMPARISON WITH EXISTING TECHNOLOGIES

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This section evaluates the efficiency of the proposed inverter by calculating switching and conduction losses, assuming ideal transformers in this study. The switching frequency $\left({F}_{\mathrm{s}}\right)$ is maintained at 20 kHz, and the fundamental frequency $\left({F}_{0}\right)$ at 60Hz. The load power factor (pf) is unity to ensure that the maximum active power is delivered to the load. This condition is applied to all inverters, including NPC, FC, CHB, and the proposed topology.

The proposed converter is compared against the current technologies: specifically, three-phase twelve-switch NPC, FC, and CHB converters. All converters utilize the same IGBT switch, Infineon FF600R12ME4, with a voltage rating of 1200V, a current rating of 600A, and a maximum junction temperature of 150℃. The numerical evaluation of converter losses is conducted using the PSIM thermal module. This module dynamically assesses the switching and conduction losses by identifying switching instants and conduction periods, summing the losses over a fundamental period. A comparison of efficiency for the proposed converter and the NPC, FC, and CHB converters is illustrated in Fig. 8(a). The efficiency of the proposed converter and other topologies remains high for lower load current, with a maximum efficiency of 99.60% recorded for the proposed converter at a power factor of one. However, existing technologies NPC, FC, and CHB exhibit lower efficiency compared to the proposed converter under higher load conditions. Nevertheless, the proposed converter maintains a high efficiency of 99% for all load conditions. Fig. 8(b) illustrates the conduction loss breakdowns and compares them with the proposed converter and the NPC, FC, and CHB converters. Similarly, Fig. 8(c) presents the same information but for the switching loss breakdowns. Fig. 8(c) indicates that the proposed converter exhibits the minimum switching losses compared to all other topologies under various loading conditions, thereby enhancing the overall converter efficiency. The proposed inverter has been compared against existing three-phase inverter technologies in terms of the total number of components used to build each converter, as summarized in Table V. The proposed topology uses fewer components compared to the Neutral Point Clamped (NPC) inverter and the topology proposed in [13]. Additionally, it uses the same number of components as the Flying Capacitor (FC) inverter but without the need for electrolytic capacitors. The reduction in the number of components not only decreases system losses but also reduces the production cost of the inverter. This contributes to enhancing the efficiency and cost-effectiveness, making the proposed inverter an attractive solution for modern power electronics applications.

VII. Conclusion

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This paper presents an inverter that addresses the limitations of existing multi-level inverter (MLI) technologies for applications where high fundamental frequency is required. These limitations include high switching losses due to a high carrier switching frequency and the complexity of modulation schemes necessary to maximize source utilization. The proposed inverter increases the utilization of the DC source, offering a peak phase voltage of $5{V}_{\mathrm{{dc}}}/3$, which consistently remains higher than the DC link voltage. Operating with higher efficiency over a wide range of frequencies, the proposed inverter outperforms the current MLIs, including neutral point clamped (NPC), flying capacitor (FC), and cascaded H-bridge (CHB), all of which exhibit lower efficiency at the same fundamental frequency. The paper presents a comprehensive design and analysis of the proposed planar transformers, including layer arrangements, materials, and connections. Detailed experimental and simulation results are provided to validate the overall operation and efficiency of the proposed inverter.

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doi: 10.24295/CPSSTPEA.2024.00011

Receive Date：2024-01-03
Online Date：2025-07-05
Published：2024-09-10

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Received：2024-01-03
Revised：2024-05-28
Accepted：2024-06-19

Affiliations

Purdue University Purdue School of Engineering and Technology Indianapolis 46202-5143 United States

Corresponding:

Haitham Kanakri.

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表12种不同金属材料的力学参数

科 Family	属数 Number of genus	种数 Number of species	占总种数比例 Percentage of total species (%)	属 Genus	种数 Number of species	占总种数比例 Percentage of total species (%)
鹅膏菌科Amanitaceae	2	11	5.26	鹅膏菌属 Amanita	10	4.78
小菇科 Mycenaceae	2	12	5.74	丝盖伞属 Inocybe	5	2.39
多孔菌科 Polyporaceae	8	14	6.70	蜡蘑属 Laccaria	5	2.39
红菇科 Russulaceae	3	23	11.00	小皮伞属 Marasmius	6	2.87
				小菇属 Mycena	11	5.26
				光柄菇属 Pluteus	5	2.39
				红菇属 Russula	17	8.13
				栓菌属 Trametes	5	2.39

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TABLE I Table of Variables Indicating the Operation of the Proposed TOPOLOGY IN TWELVE STEPS

Step	S₁	S₂	S₃	S₄	S₅	S₆	Starting	Ending
1	0	1	1	0	0	1	${0}^{ \circ }$	${30}^{ \circ }$
2	0	1	1	0	1	1	${30}^{ \circ }$	${60}^{ \circ }$
3	0	1	1	0	1	0	${60}^{ \circ }$	${90}^{ \circ }$
4	0	1	0	0	1	0	${90}^{ \circ }$	${120}^{ \circ }$
5	0	1	0	1	1	0	${120}^{ \circ }$	${150}^{ \circ }$
6	1	1	0	1	1	0	${150}^{ \circ }$	${180}^{ \circ }$
7	1	0	0	1	1	0	${180}^{ \circ }$	${210}^{ \circ }$
8	1	0	0	1	0	0	${210}^{ \circ }$	${240}^{ \circ }$
9	1	0	0	1	0	1	${240}^{ \circ }$	${270}^{ \circ }$
10	1	0	1	1	0	1	${270}^{ \circ }$	${300}^{ \circ }$
11	1	0	1	0	0	1	${300}^{ \circ }$	${330}^{ \circ }$
12	0	0	1	0	0	1	${330}^{ \circ }$	${360}^{ \circ }$

TABLE II The Phase and Line Voltages of the Proposed Topology in Twelve Steps

Step	v_un	v_vn	v_wn	v_uv	v_vw	v_wu
1	$- {V}_{\mathrm{{dc}}}/3$	$\left( {5{V}_{\mathrm{{dc}}}}\right) /3$	$- \left( {4{V}_{\mathrm{{dc}}}}\right) /3$	$- 3{V}_{\mathrm{{dc}}}$	$2{V}_{\mathrm{{dc}}}$	${V}_{\mathrm{{dc}}}$
2	$- \left( {2{V}_{\mathrm{{dc}}}}\right) /3$	$\left( {4{V}_{\mathrm{{dc}}}}\right) /3$	$- \left( {2{V}_{\mathrm{{dc}}}}\right) /3$	$- 3{V}_{{}_{\mathrm{{dc}}}}$	${V}_{\mathrm{{dc}}}$	$2{V}_{\mathrm{{dc}}}$
3	$- \left( {5{V}_{\mathrm{{dc}}}}\right) /3$	$\left( {4{V}_{\mathrm{{dc}}}}\right) /3$	${V}_{{}_{\mathrm{{dc}}}}$ /3	$- 2{V}_{\mathrm{{dc}}}$	$- {V}_{\mathrm{{dc}}}$	$3{V}_{\mathrm{{dc}}}$
4	$- \left( {4{V}_{\mathrm{{dc}}}}\right) /3$	$\left( {2{V}_{\mathrm{{dc}}}}\right) /3$	$\left( {2{V}_{\mathrm{{dc}}}}\right) /3$	$- {V}_{\mathrm{{dc}}}$	-2 ${V}_{\mathrm{{dc}}}$	$3{V}_{\mathrm{{dc}}}$
5	$- \left( {4{V}_{\mathrm{{dc}}}}\right) /3$	$- {V}_{\mathrm{{dc}}}/3$	(5 ${V}_{\mathrm{{dc}}}$)/3	${V}_{\mathrm{{dc}}}$	$- 3{V}_{\mathrm{{dc}}}$	$2{V}_{\mathrm{{dc}}}$
6	$- \left( {2{V}_{\mathrm{{dc}}}}\right) /3$	$- \left( {2{V}_{\mathrm{{dc}}}}\right) /3$	$\left( {4{V}_{\mathrm{{dc}}}}\right) /3$	$2{V}_{\mathrm{{dc}}}$	$- 3{V}_{\mathrm{{dc}}}$	${V}_{\mathrm{{dc}}}$
7	${V}_{\mathrm{{dc}}}/3$	$- \left( {5{V}_{\mathrm{{dc}}}}\right) /3$	$\left( {4{V}_{\mathrm{{dc}}}}\right) /3$	$3{V}_{\mathrm{{dc}}}$	$- 2{V}_{\mathrm{{dc}}}$	$- {V}_{\mathrm{{dc}}}$
8	$\left( {2{V}_{\mathrm{{dc}}}}\right) /3$	$- \left( {4{V}_{\mathrm{{dc}}}}\right) /3$	$\left( {2{V}_{\mathrm{{dc}}}}\right) /3$	$3{V}_{\mathrm{{dc}}}$	$- {V}_{\mathrm{{dc}}}$	$- 2{V}_{\mathrm{{dc}}}$
9	$\left( {5{V}_{\mathrm{{dc}}}}\right) /3$	$- \left( {4{V}_{\mathrm{{dc}}}}\right) /3$	$- {V}_{\mathrm{{dc}}}/3$	$2{V}_{\mathrm{{dc}}}$	${V}_{\mathrm{{dc}}}$	$- 3{V}_{\mathrm{{dc}}}$
10	$\left( {4{V}_{\mathrm{{dc}}}}\right) /3$	$- \left( {2{V}_{\mathrm{{dc}}}}\right) /3$	$- \left( {2{V}_{\mathrm{{dc}}}}\right) /3$	${V}_{\mathrm{{dc}}}$	$2{V}_{\mathrm{{dc}}}$	$- 3{V}_{{}_{\mathrm{{dc}}}}$
11	$\left( {4{V}_{\mathrm{{dc}}}}\right) /3$	${V}_{\mathrm{{dc}}}/3$	$- \left( {5{V}_{\mathrm{{dc}}}}\right) /3$	$- {V}_{\mathrm{{dc}}}$	$3{V}_{\mathrm{{dc}}}$	$- 2{V}_{\mathrm{{dc}}}$
12	$\left( {2{V}_{\mathrm{{dc}}}}\right) /3$	$\left( {2{V}_{\mathrm{{dc}}}}\right) /3$	$- \left( {4{V}_{\mathrm{{dc}}}}\right) /3$	$- 2{V}_{\mathrm{{dc}}}$	$3{V}_{\mathrm{{dc}}}$	$- {V}_{\mathrm{{dc}}}$

TABLE III TSI Planar Transformer Design Requirements

Design Parameter	Value
Output Power ${P}_{\mathrm{o}}/\mathrm{{kW}}$	3.5
Output Current ${I}_{\mathrm{o}}/\mathrm{A}$	1.50
Frequency $f/\mathrm{{kHz}}$	5
Efficiency $\eta /\%$	98
Temperature rise $\Delta {T}^{o}\mathrm{C}$	10
Flux density ${B}_{\mathrm{m}}/\mathrm{{mT}}$	300
Turns Ratio N	1:1
Primary Voltage/V	130

TABLE IV Proposed Planar Transformer Parameters

Parameter	Value
Magnetizing Inductance $/\mu \mathrm{H}$	848.22
Leakage Inductance $/\mu \mathrm{H}$ @ $5\mathrm{{kHz}}$	0.197
dc Resistance $/\mathrm{m}\Omega$	62.23
AC Resistance $/\mathrm{m}\Omega$ @ $5\mathrm{{kHz}}$	165
${C}_{11}/\mathrm{{pF}}$	793.48
${C}_{12}$ /pF	54.86
${C}_{\mathrm{o}{12}}/\mathrm{{nF}}$	1.64

TABLE V Comparison of Component Count in Proposed and Existing Three-Phase Inverters Technology

Configuration	IGBTs	Diodes	Cap	DC Sources	TR	Total
NPC	12	18	2	1	0	33
FC	12	12	3	1	0	28
CHB	12	12	0	3	0	27
[13]	12	36	3	1	0	52
Proposed	12	12	0	1	3	28

Fig. 1. The proposed twelve-step voltage source inverter (TSI).

Fig. 2. (a) Integrated prototype of electrically powered high-lift system adapted from [12].(b) Drawing shows the power active high-lift system integrated into a wing of an aircraft, adapted from [14].

Fig. 3. (a) Proposed topology of twelve-step three-phase six-level inverter (TSI), the DC-link capacitors $C$ are utilized exclusively for modeling purposes and are not required for the system’s operation.(b) TSI equivalent circuit.(c) TSI main voltages for phase-u.(d) Three-phase six-level phase load voltage waveform in twelve-steps.

Fig. 4. (a) Typical EE-planar transformer showing the EE-core, primary winding, insulation and secondary winding layers.(b) The E core section of EE-core shows the window area ${W}_{a}$ definition and the core cross-sectional area ${A}_{c}$ .(c) Graphical representation of (28) and the ${K}_{t}= {4.0}$ factor for square voltage input type of shape.(d) Ferroxcube ES8/11/38-3F4 selected core with dimensions in mm indicated by letters A, B, C, D, E and F.(e) 3D view of the proposed transformer in Ansys MAXWEL simulation software.(f) Equivalent circuit model of the proposed transformer with the intra and inter capacitance values.(g) The main connections and layer arrangement of the proposed transformer.

Fig. 5. (a) Photo of the experimental setup of the twelve-step inverter with the proposed planar transformers.(b) Proposed single planar phase transformer.(c) Simulation results: TSI main voltage for phase-u.(d) Simulation results: phase voltages ${v}_{\mathrm{{un}}},{v}_{\mathrm{{un}}},{v}_{\mathrm{{un}}}$ .(e) Simulation results: phase currents ${i}_{\mathrm{u}},{i}_{\mathrm{v}},{i}_{\mathrm{w}}$ and the input DC current.(f) Experimental results: TSI main voltage for phase-u.(g) Experimental results: Phase voltages ${v}_{un},{v}_{vn},{v}_{vn}$ .(h) Experimental results: Phase currents ${i}_{v},{i}_{v}$, ${i}_{\mathrm{w}}$ and the input dc current.

Fig. 6. Transient of the phase voltage with three, four, and six levels:(a) simulation and (b) experimental results.

Fig. 7. Phasor diagram for different modes of operation:(a) three steps,(b) six steps,(c) twelve steps.

Fig. 8. Comparison between the proposed inverter and other multi-levels inverters.(a) Efficiency analysis.(b) Conduction losses.(c) Switching losses.

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