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A Constant Common Mode Voltage Single-Phase Five-Level Transformerless PV Inverter Considering the Effect of Switch Device Junction Capacitance
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MLN VITAL1, Venu SONTI1, Yam P. SIWAKOTI2, Sze Sing LEE3, Sachin JAIN1
CPSS Transactions on Power Electronics and Applications | 2024, 9(3) : 313 - 324
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CPSS Transactions on Power Electronics and Applications | 2024, 9(3): 313-324
• Papers •
A Constant Common Mode Voltage Single-Phase Five-Level Transformerless PV Inverter Considering the Effect of Switch Device Junction Capacitance
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MLN VITAL1, Venu SONTI1, Yam P. SIWAKOTI2, Sze Sing LEE3, Sachin JAIN1
Affiliations
  • 1 National Institute of Technology Raipur Department of Electrical Engineering Raipur 492010 India
  • 2 University of Technology Sydney Faculty of Engineering and Information Technology Sydney 2007 Australia
  • 3 Newcastle University Singapore 567739 Singapore

    • MLN Vital received his B.Tech. degree in Electrical and Electronics Engineering from JNTU, Hyderabad in the year 2008 and M.Tech. degree in Power Electronics from VIT university, Vellore in the year 2010. He is currently doing part-time Ph.D. at National Institute of Technology (NIT) Raipur. His areas of interest include multilevel inverter applications for Solar PV applications.

    Venu Sonti received B.Tech. degree in Electrical and Electronics Engineering from the Koneru Lakshmaiah College of Engineering, Guntur, India in the year 2011 and M.Tech. degree in Power Electronics and Drives from the National Institute of Technology Warangal, Warangal, India in the year 2013 and Ph.D. degree from National Institute of Technology Warangal, India. Currently, he is working as an Assistant Professor in National Institute of Technology Raipur, India. His research interests include the grid-connected inverter for renewable energy generation.

    Yam P. Siwakoti received the B.Tech. degree in electrical engineering from the National Institute of Technology, Hamirpur, India, in 2005, the master's degree in electrical power engineering from the Norwegian University of Science and Technology, Trondheim, Norway, and Kathmandu University, Dhulikhel, Nepal, in 2010, and the Ph.D. degree in electronic engineering from Macquarie University, Sydney, NSW, Australia, in 2014. During 2014-2016, he was a Postdoctoral Fellow with the Department of Energy Technology, Aalborg University, Aalborg, Denmark. During 2017-2018, he was a Visiting Scientist with the Fraunhofer Institute for Solar Energy Systems, Freiburg, Germany. His research was the recipient of the series of awards including the most prestigious Friedrich Wilhelm Bessel Research Award from Alexander von Humboldt Foundation, Germany, in 2022, and the Green Talent Award from the Federal Ministry of Education and Research, Germany, in 2016. Dr. Siwakoti is currently an Associate Professor with the Faculty of Engineering and Information Technology, University of Technology Sydney. He is an Associate Editor for IEEE Transactions on Power Electronics, IEEE Transactions on Industrial Electronics and IEEE Journal of Emerging and Selected Topics in Power Electronics.

    Sze Sing Lee received the B.Eng. (with Hons.) and Ph.D. degrees in electrical engineering from Universiti Sains Malaysia, George Town, Malaysia, in 2010 and 2013, respectively. From 2014 to 2019, he was a Lecturer/Assistant Professor with the University of Southampton Malaysia Campus, Gelang Patah, Malaysia. From 2018 to 2019, he was a Visiting Research Professor with Ajou University, Suwon, South Korea. He is currently an Assistant Professor with Newcastle University, Singapore. He is also a Chartered Engineer registered with the Engineering Council, U.K. His research interests include power converter/inverter topologies and their control strategies. Dr. Lee is also an Associate Editor for IEEE Transactions on Industrial Electronics and IEEE Access, and a Guest Associate Editor of IEEE Transactions on Power Electronics.

    Sachin Jain received the B.E. degree in electrical engineering from the Bhilai Institute of Technology, Bhilai, India, in 2000, the M. Tech. degree in integrated power systems from the Visvesvaraya National Institute of Technology, Nagpur, India, in 2002, and the Ph.D. degree in power electronics from the Indian Institute of Technology, Bombay, Mumbai, India, in 2007. He is currently working as an Associate Professor with the National Institute of Technology, Raipur, India. Before joining NIT-RR, he had worked with NIT-Warangal as an Associate Professor and the Solar Energy Business Group of Schneider Electric as a Senior Design Engineer in the Research and Development Department, Bangalore. His research interests include power electronics applications in nonconventional energy conditioning, power quality, and distributed generation.

Published: 2024-09-10 doi: 10.24295/CPSSTPEA.2024.00010
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Constant common mode voltage (CCMV) is critical in Solar Photovoltaic (SPV) systems. Maintaining CCMV further eliminates the voltage transitions across the parasitic capacitance of the PV panel, making it a lowfrequency output voltage waveform. This further reduces the CMC and leakage current in the SPV systems. This paper presents a CCMV switched capacitor PV inverter configuration that maintains a lowfrequency terminal voltage while considering the effect of switch device junction capacitance (SDJC). Thus, the proposed configuration eliminates the transitions in the common mode and terminal voltage due to the SDJC. The two switched capacitors employed in the proposed configuration are charged and discharged within each switching period, supporting the selfcharge balance feature apart from low voltage and RMS current rating, reducing its size and value. Further, the proposed system effectively utilizes the PV source as switch capacitors and the DCbus buffer capacitor across the PV source comes in parallel in each switching period. The proposed configuration can also operate at lower modulation indices, generating three levels with CCMV. A new mathematical analysis considering SDJC is given for the derivation of expression for CMV and terminal voltage, which is further verified using simulation and experimental results.

Five-level inverter common mode voltage  /  switched capacitor  /  transformerless PV inverter  /  leakage current
MLN VITAL, Venu SONTI, Yam P. SIWAKOTI, Sze Sing LEE, Sachin JAIN. A Constant Common Mode Voltage Single-Phase Five-Level Transformerless PV Inverter Considering the Effect of Switch Device Junction Capacitance[J]. CPSS Transactions on Power Electronics and Applications, 2024 , 9 (3) : 313 -324 . DOI: 10.24295/CPSSTPEA.2024.00010
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I. INTRODUCTION
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IN N recent times, transformerless PV inverters (TPVIs)[1]-[12] which eliminates the transformer between PV source and grid have earned some interest among researchers worldwide. Due to the absence of galvanic isolation in the system, TPVIs have advantages like reduced weight, reduced power conversion stages, high efficiency, and reduced cost. However, alleviating common mode current (CMC) and leakage current flowing through the parasitic capacitance in the PV systems remains a critical issue that must be taken care of during the inverter design [1]. The flow of CMC and leakage current in the TPVI creates serious concerns like distortion of grid current, increased conducted and radiated EMI issues, additional losses in PV panels, deterioration of PV panel characteristics, etc. Due to this, it is very critical to minimize or maintain the magnitude of CMC and leakage currents flowing in the TPVI below the prescribed limit. One such limit for leakage current is mentioned in the German standard VDE0126-1-1 [13].
The CMC and leakage current flowing in the TPVI are mainly due to the high-frequency transitions (HFTs) in the common mode voltage (CMV)[13]. Thus, it is essential to eliminate such HFTs in CMV to minimize the CMC and leakage currents. Therefore, controlling the magnitude of CMC and leakage current by maintaining the constant common mode voltage (CCMV)[13] is vital in TPVI systems. Maintaining the CCMV eliminates the common mode current and reduces the leakage current. This can be attributed to the fact that for a CCMV, the voltage across the PV panel parasitic capacitance will be low-frequency [14] in nature. This voltage across the PV panel parasitic capacitance is normally termed as the terminal voltage. The PV panel parasitic capacitance normally offers high impedance to the low-frequency terminal voltage, which reduces the magnitude of the leakage current. Apart from the minimization of CMC and leakage, the harmonic free current with low THD needs to be injected into the grid. Thus, there is a requirement of multi-level inverter topology with CCMV. In the literature, the researchers have provided various solutions for addressing the above-mentioned concerns.
Xiaoqiang et al.[15] given an interesting five-level TPVI topology to tackle the issue of terminal and common mode voltage (TCMV) transitions. The given multi-level topology has two individual H5 cascaded inverters. The given topology generates five levels output voltage by using ten switches and two independent symmetrical PV sources. The given topology suffers from the adverse effects of switch device junction capacitance (SDJC), resulting in HFTs in the common mode voltage (CMV). Further, no analysis on CMV, while taking into account the effect of the SDJC is given. Also, the given topology requires two independent symmetrical PV sources with equal operating voltage to obtain the five levels in the inverter output voltage.
Sathik et al.[16] given another interesting five-level inverter topology for addressing the issue of leakage current in TPVIs. The given five-level inverter uses nine power semiconductor devices and two switched capacitors to obtain the five levels in the inverter output voltage with a single PV source. The given topology has the benefit of twice the voltage-boosting capability with effective PV source utilization. However, the presence of diodes in the five-level inverter limits the reactive power capability of the given configuration. Further, the given topology suffers from the problem of SDJC at zero voltage level. Due to the SDJC, the TCMV have different voltage values both during active and zero state. Different voltage values leads to high-frequency switching transitions in TCMV. Further, the given solution reduces the CMC and leakage currents by minimizing the transitions in the CMV, but does not completely eliminate it.
Another interesting five-level inverter topology with CCMV is given by Xiaonan et al.[17]. The given five-level TPVI topology uses twelve switches, two flying capacitors and a single PV source for the generation of five-level output voltage. The given topology reduces the leakage current by maintaining CCMV. But special care or strategy is required to maintain VPV/4 (one-fourth of DC bus or PV voltage) across the flying capacitor. Thus, a complex control circuit is always required to charge the flying capacitors. Bharath et al.[18] given another interesting inverter topology with five-level output with the alleviation of leakage current in PV systems. The given inverter uses nine semiconductor devices and two switched capacitors to obtain the five-level output with CCMV. However, the switched capacitors used in the five-level inverter do not charge for a period of 60° of output voltage. In other words, the longest discharge period for the switched capacitors is 60°. Due to high discharge time, the size of switched capacitors required would be very large. In the given topology, the switched capacitors also draw high charging currents from the PV source and there is no self-charge balancing feature for the switched capacitors. Also, in the given five-level inverter, the PV source remains idle for a period of 120° in the inverter output voltage. As a result, the given five-level inverter has less DC bus voltage utilization. In addition to this, the size of the buffer capacitor required at the output of the PV source will be large. Also, the given five-level inverter will not work for the modulation index less than 0.5 because of the absence of charging state for capacitors during 0 voltage level and may limit its operation for a stand-alone system.
Based on the above there is a requirement of the five-level inverter topology, which has below features:
1. Should maintain a CCMV for all the output voltage levels by taking the effect of SDJC into account.
2. Should require a low value and low voltage rating switched capacitors.
3. PWM strategy should be such that the inherent self-charge balancing property for switch capacitors should be there.
4. PV source should be utilized during each switching period ${T}_{\mathrm{s}}$ in the complete fundamental period ${T}_{\mathrm{g}}$. This also results in a low PV voltage ripple leading to its maximum utilization.
5. Inverter should be able to operate for all modulation index with CCMV.
The given manuscript proposes the solution for CCMV five-level PV inverter topology with all the above-given features. Further in this manuscript, the expression for TCMV using the switching function including the SDJC effect is also presented. The complete manuscript is divided into six sections. Section II gives details of the operation of the proposed five-level TPVI topology. Section III gives the details of the effect of SDJC on CMV in the proposed five-level TPVI topology. The analysis of TCMV for the proposed five-level TPVI topology is discussed in Section IV. The simulation and experimental results of the proposed five-level TPVI topology is discussed in Section V and Section VI.
II. Working Principle and Operation of Proposed FIVE-LEVEL INVERTER
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Fig. 1 shows the circuit schematic of the proposed five-level inverter. The proposed five-level inverter is developed by cascading two converter units namely Conv-I and Conv-II. The Conv-II [19] shown in Fig. 1 is a three-level inverter. By cascading the Conv-I with Conv-II, the number of levels in the output voltage of the proposed inverter is extended from three to five. Apart from increased number of levels in output voltage, the proposed five-level inverter also alleviates the leakage current by maintaining CCMV during all five levels in inverter output voltage.
The Conv-I constitutes of five switches ${\mathrm{S}}_{1}$ to ${\mathrm{S}}_{5}$ and two switched capacitors, ${C}_{\mathrm{S}1}$ and ${C}_{\mathrm{S}2}$. Among the five switches, ${\mathrm{S}}_{1}$ and ${\mathrm{S}}_{2}$ are called decoupling switches. These switches connect and disconnect the PV source to input terminals (i.e., the terminal points ” $\mathrm{m}$ ” and ” $\mathrm{n}$ “) of the Conv-II. To generate a voltage value of VPN in Conv-I the switch ${\mathrm{S}}_{4}$ along with the decoupling switches ${\mathrm{S}}_{1}$ and ${\mathrm{S}}_{2}$ are turned ON. When three switches are turned ON for the voltage level VPN at Conv-I output, the two switched capacitors, ${C}_{\mathrm{S}1}$ and ${C}_{\mathrm{S}2}$ are connected in series and their series connection comes in parallel with the input PV source. The switched capacitors are charged with input PV source when connected across it. Thus, the overall buffer capacitor value across the PV source increases during the voltage level VPN at Conv-I output. The voltage level VPN/2 in Conv-I is generated by turning ON the other pair of switches ${\mathrm{S}}_{3}$, and ${\mathrm{S}}_{5}$ and rest of the other switches in Conv-I are turned OFF. When switches ${\mathrm{S}}_{3}$, and ${\mathrm{S}}_{5}$ are turned ON, the switched capacitors, ${C}_{\mathrm{S}1}$ and ${C}_{\mathrm{S}2}$ with an equal voltage of VPN/2 are connected in parallel to generate a voltage level of VPN/2. Thus, the switches, ${\mathrm{S}}_{3}$ and ${\mathrm{S}}_{5}$ in Conv-I, operate in complementary mode to the switches, ${\mathrm{S}}_{1},{\mathrm{\;S}}_{2}$, and ${\mathrm{S}}_{4}$ to generate two voltage levels of VPN/2 and VPV respectively.
The input terminals (“m” and “n”) of the Conv-II become the output terminals of the Conv-I [19]. Thus, the Conv-II gets its input from Conv-I. The Conv-II converts the generated voltage levels in Conv-I into required AC at the inverter output voltage, apart from generating 0 level at the inverter output voltage. The Conv-II is a H6 [19] inverter formed by the six switches, ${\mathrm{S}}_{6}$ to ${\mathrm{S}}_{11}$. The Conv-I output voltage levels of $+{V}_{\mathrm{{PV}}}$ and +VPN/2 get converted into inverter output voltage ${v}_{\mathrm{{yz}}}$ with $+{V}_{\mathrm{{PV}}}$ and +VPN/2 values respectively by turning ON the switches, ${\mathrm{S}}_{6},{\mathrm{\;S}}_{8}$ and ${\mathrm{S}}_{11}$ in the Conv-II. Similarly, Conv-I output voltage levels of $+{V}_{\mathrm{{PV}}}$ and +VPN/2 get converted into inverter output voltage ${v}_{\mathrm{{yz}}}$ with $-{V}_{\mathrm{{PV}}}$ and -VPN/2 values, respectively by turning $\mathrm{{ON}}$ the switches, ${\mathrm{S}}_{7}$ and ${\mathrm{S}}_{9}$ in the Conv-II. During the 0 voltage level, the switches ${\mathrm{S}}_{8}$ and ${\mathrm{S}}_{10}$ in Conv-II are turned $\mathrm{{ON}}$ to freewheel output current through these switches. Thus, during the levels of 0 and $\pm {V}_{\mathrm{{PV}}}$ across the inverter output, the two identical switched capacitors, ${C}_{\mathrm{S}1}$ and ${C}_{\mathrm{S}2}$ are charged in series by input PV source with an equal voltage of VPN/2. This further helps in reducing PV voltage ripple. During the voltage level of VPN/2 at Conv-I output, the two switched capacitors, ${C}_{\mathrm{S}1}$ and ${C}_{\mathrm{S}2}$ are connected in parallel across the output load. The switched capacitors are discharged when connected is parallel with output load. Thus, in each switching period of the inverter the switch capacitors are charged and discharged simultaneously. This further helps in reducing the size and current rating of the switched capacitor. Above all, it further supports the effective utilization of the PV source, as 0 or $\pm {V}_{\mathrm{{PV}}}$ inverter output voltage levels exist in each switching period of the output voltage cycle.
Since, the switch capacitors are discharged at the voltage levels of $\pm {V}_{\mathrm{{PV}}}/2$, the value of current flowing through the switched capacitors, ${C}_{\mathrm{S}1}$ and ${C}_{\mathrm{S}2}$ will be less in the proposed inverter. The parallel operation of the switched capacitors ${C}_{\mathrm{S}1}$ and ${C}_{\mathrm{S}2}$ during discharge further supports in reducing its current rating. This action helps in minimizing both voltage and current ripple in switched capacitors. Further, during the voltage levels 0 and $\pm {V}_{\mathrm{{PV}}}$, the buffer capacitor ${C}_{\mathrm{{PV}}}$ (across the PV source) comes in parallel to the series connected switched capacitors ${C}_{\mathrm{S}1}$ and ${C}_{\mathrm{S}2}$. As a result, the current ripple in the switched and buffer capacitors during the voltage levels 0 and $\pm {V}_{\mathrm{{PV}}}$ is minimized. In this way, the proposed topology using switched capacitors ${C}_{\mathrm{S}1}$ and ${C}_{\mathrm{S}2}$ generates five levels in the inverter output voltage. Further, the charging and discharging current of the switch capacitors is less, apart from less voltage ripple. Apart from the less voltage ripple and less charging and discharging current, the switched capacitors ${C}_{\mathrm{S}1}$ and ${C}_{\mathrm{S}2}$ have self-charge balance property. Fig. 2 shows the waveform of the output voltage of the five-level inverter along with the charging and discharging of the switched capacitors ${C}_{\mathrm{S}1}$ and ${C}_{\mathrm{S}2}$. From Fig. 2, it can be observed that the two switched capacitors ${C}_{\mathrm{S}1}$ and ${C}_{\mathrm{S}2}$ are charged in one voltage level and discharged in the subsequent output voltage level. This pattern will continue for the entire cycle of the output voltage. So, for any required output voltage, the two switched capacitors ${C}_{\mathrm{S}1}$ and ${C}_{\mathrm{S}2}$ have a self-charge balancing feature. Further, due to subsequent charging and discharging of the switched capacitors, the longest discharge period for the switched capacitors ${C}_{\mathrm{S}1}$ and ${C}_{\mathrm{S}2}$ is the switching time period. Due to this, the size of the switched capacitors ${C}_{\mathrm{S}1}$ and ${C}_{\mathrm{S}2}$ will be very less [18]. Therefore, by increasing the switching frequency, the size of switched capacitors ${C}_{\mathrm{S}1}$ and ${C}_{\mathrm{S}2}$ along with their current spike magnitude can be reduced further. Also, the two switched capacitors ${C}_{\mathrm{S}1}$ and ${C}_{\mathrm{S}2}$ are discharged in parallel during the voltage levels $\pm {V}_{\mathrm{{PV}}}/2$. This results in the reduction of the value of switched capacitors to half. Further, due to the charging of switched capacitors ${C}_{\mathrm{S}1}$ and ${C}_{\mathrm{S}2}$ during the 0 voltage level, the proposed inverter can generate three levels (${\pm}$VPV/2 and 0) for the lower modulation indices. Therefore, the proposed topology can be even operated at lower modulation indices.
The Conv-II output terminals are connected to grid ${v}_{\mathrm{g}}$ through a filter as shown in Fig. 1. The LCL filter is used to smoothen the inverter output current. The terms ${L}_{\mathrm{{if}}}$ and ${L}_{\mathrm{{gf}}}$ in the LCL filter refer to the filter inductor at the inverter and grid side respectively. The term ${C}_{\mathrm{f}}$ represents the filter capacitor. The terms ${R}_{\mathrm{f}}, R$ and ${R}_{\mathrm{g}}$ represent the damping resistor in the filter, filter resistor, and the ground resistor respectively. The terms ${i}_{\mathrm{{yz}}},{i}_{\mathrm{g}}$ and ${i}_{\mathrm{f}}$ denote the inverter output current, grid current and the filter shunt branch current respectively. The series combination of parasitic capacitance ${C}_{\mathrm{{pc}}}$ and resistance ${R}_{\mathrm{{pc}}}$ of the PV source is connected between the PV “u” and ground “g” terminal nodes as shown in Fig. 1. The parasitic resistance and capacitance are denoted by terms ${R}_{\mathrm{{pc}}}$ and ${C}_{\mathrm{{pc}}}$ respectively. The ${i}_{\mathrm{{cpc}}}$ is the current flowing through this parasitic branch. The voltage ${v}_{\mathrm{{ug}}}$ is called the terminal voltage of the PV source. The terminal voltage is a function of the common mode and the grid voltage. The common mode is the average of the inverter pole voltages [20]-[21]. Usually while calculating the inverter pole voltages, the effect of the junction capacitance across power semiconductor switches that are in the turn OFF state is neglected. But practically, it can affect inverter pole voltages during the turn OFF condition typically in DC decoupled configuration [15]. The transitions in the TCMV waveforms, can be attributed to the effect of SDJC during the turn-off state. The proposed DC decoupled five-level inverter using PWM technique eliminates this effect and restricts the HFTs in the TCMV. Due to the absence of these HFTs, the proposed five-level inverter with the given PWM technique generates a low-frequency terminal voltage and CCMV. The low-frequency terminal voltage reduces the magnitude of the leakage current due to high impedance value of parasitic capacitance in the PV system. Thus, the proposed topology attenuates leakage current magnitude in the PV systems. The magnitude of leakage current is further alleviated due to the additional restriction of transitions in the TCMV because of SDJC effect. The details of restriction of transitions in the TCMV due to SDJC is explained in the next section.
III. EFFECT OF SWITCH DEVICE JUNCTION CAPACITANCE ON CMV IN THE PROPOSED FIVE-LEVEL MLI
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The proposed solution, as discussed, alleviates the both leakage and common mode current. This is obtained by maintaining the low-frequency terminal voltage and CCMV by considering the effect of the SDJC for the DC decoupled configuration. The effect of SDJC on TCMV will exist, whenever the corresponding switch is turned OFF. Fig. 3 shows the circuit of the proposed five-level inverter along with their SDJC. The term ${C}_{i}$ denotes the junction capacitance across switch ${\mathrm{S}}_{i}$, where $i = 1,2,\ldots,{11}$. The SDJC are shown in the red color of Fig. 3. In Conv-I, the series connected device junction capacitors ${C}_{3}$ and ${C}_{4}$ comes in parallel to the switched capacitor ${C}_{\mathrm{S}1}$ and the series connected device junction capacitors ${C}_{4}$ and ${C}_{5}$ comes in parallel to the switched capacitor ${C}_{\mathrm{S}2}$ during circuit operation. As the values of these device junction capacitors are very small when compared with switched capacitors ${C}_{\mathrm{S}1}$ and ${C}_{\mathrm{S}2}$, their effect in the circuit can be neglected as can be observed in Fig. 3. The effect of SDJC on the proposed inverter topology need to be analyzed for all the output voltage levels.
Fig. 4 shows the different modes of operation of the proposed inverter considering their SDJC. For simplicity, the value of the SDJC is assumed to be equal. The effect of SDJC on the CMV which is the average of two pole voltages ${v}_{\mathrm{{yw}}}$ and ${v}_{\mathrm{{zw}}}$ can be obtained by observing the magnitude of pole voltages ${v}_{\mathrm{{yw}}}$ and ${v}_{\mathrm{{zw}}}$ for each output voltage level. Table I shows the switching states of the individual switches along with the pole voltages ${v}_{\mathrm{{yw}}},{v}_{\mathrm{{zw}}}$, output voltage ${v}_{\mathrm{{yz}}}$ and common mode voltage ${v}_{\mathrm{{cm}}}$. During the output voltage levels $+{V}_{\mathrm{{PV}}}$ and $-{V}_{\mathrm{{PV}}}$ as shown in Fig. 4(a) and (d), the value CMV ${V}_{\mathrm{{cm}}}$ is equal to VPN/2. For the output voltage levels +VPN/2 and -VPN/2 shown in Fig. 4(b) and (e), due to the turn OFF the switches ${S}_{1}$ and ${S}_{2}$ in Conv-I, a voltage of VPN/4 is appeared across the SDJC ${C}_{1}$ and ${C}_{2}$. Therefore, the pole voltages ${v}_{\mathrm{{yw}}}$ and ${v}_{\mathrm{{zw}}}$ will attain the values 3VPN and VPN/4 for the output voltage +VPN/2 and the pole voltages ${v}_{\mathrm{{yw}}}$ and ${v}_{\mathrm{{zw}}}$ will attain the values VPN/4 and 3VPN/4 for the output voltage -VPN/2. This helps in retaining the value of the CMV to VPN/2. During the 0 voltage level as shown in Fig. $4\left(\mathrm{c}\right)$, a pair of series combinations of the SDJC $\left({{C}_{6},{C}_{9}}\right)$ and $\left({{C}_{7},{C}_{11}}\right)$ comes in parallel with the source. This results in the equal pole voltages of VPN/2 for the ${v}_{\mathrm{{yw}}}$ and ${v}_{\mathrm{{zw}}}$ as can be seen in Fig. 4(c). Therefore, for the 0 voltage level also, the value of CMV is retained to VPN/2 in the proposed configuration. Thus, the proposed system maintains the CMV to the value of VPN/2 without being affected by the presence of SDJC. Further, the effect of SDJC on CMV and terminal voltage can also be analyzed using mathematical analysis. A mathematical analysis-based switching function concept incorporating the effect of SDJC is given in the next section.
IV. Analysis of Terminal and Common Mode Voltage
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For alleviation of CMC and leakage current through PV system parasitic capacitance, the nature of the TCMV needs to be studied. For analyzing the nature of TCMV, the switching function concept [20]-[21] is used, which also includes the effect of SDJC. Fig. 5 shows the circuit diagram of the proposed five-level inverter along with the switching function incorporated SDJC. The binary variable ${k}_{i}$ represents the switching state for the switch ${\mathrm{S}}_{i}$ where $i = 1,2,\ldots,{11}$, will have a value of either 1 or 0 representing the turn $\mathrm{{ON}}$ and turn $\mathrm{{OFF}}$ of the switch. The impedance of SDJC during the turn-on state $\left({{k}_{i}= 1}\right)$ is zero and its effect is neglected. However, during the turn-off state of switch ${S}_{i}$ the corresponding binary variable ${k}_{i}$ is equal to 0 . As a result, an impedance due to SDJC ${C}_{i}$ will appear across the switch ${\mathrm{S}}_{i}$. For simplicity, ${C}_{i}$ is taken as C for all the values of i. In Conv-I, the expression for the voltages ${v}_{\mathrm{{mn}}},{v}_{\mathrm{{um}}}$ and ${v}_{\mathrm{{nw}}}$ is given by (1) and (2).
${v}_{\mathrm{{mm}}}= {V}_{\mathrm{{PV}}}\left({{k}_{1}{k}_{2}}\right)+ \frac{{V}_{\mathrm{{PV}}}}{2}\left({{k}_{3}{k}_{5}}\right)$
${v}_{\mathrm{{um}}}= {v}_{\mathrm{{nw}}}= \frac{{v}_{\mathrm{{mm}}}- {V}_{\mathrm{{PV}}}\left({{k}_{1}{k}_{2}}\right)}{2}$
In Conv-II using the circuit analysis, the expression for the voltages ${v}_{\mathrm{{yn}}}$ and ${v}_{\mathrm{{zn}}}$ are given by
${v}_{\mathrm{{yn}}}= \frac{{v}_{\mathrm{{mn}}}\left({1 -{k}_{9}}\right)}{Den}$
${v}_{\mathrm{{zn}}}= \frac{{v}_{\mathrm{{mn}}}\left({1 -{k}_{6}}\right)}{1 +\frac{\left( 1 -{k}_{7}\right)}{\left( 1 -{k}_{11}\right)}}+ \frac{{v}_{\mathrm{{mn}}}{k}_{6}\left\lbrack \frac{Num1}{Den1}\right\rbrack }{1 +\frac{{k}_{\mathrm{c}}}{\left( 1 -{k}_{11}\right)}}$
${Den}= \left({1 -{k}_{9}}\right)+ \left({1 -{k}_{8}}\right)+ {k}_{\mathrm{a}}+ {k}_{\mathrm{b}}+ \frac{{k}_{\mathrm{b}}\left\lbrack {{k}_{\mathrm{a}}+ \left({1 -{k}_{9}}\right)+ \left({1 -{k}_{8}}\right)}\right\rbrack }{\left({1 -{k}_{11}}\right)+ {k}_{\mathrm{c}}}$
$\text{ Num }1 =\left\lbrack {{k}_{\mathrm{c}}+ \left({1 -{k}_{11}}\right)}\right\rbrack \left\lbrack {{k}_{\mathrm{a}}+ \left({1 -{k}_{8}}\right)+ \left({1 -{k}_{9}}\right)}\right\rbrack $
$\text{Den}1 =\left\lbrack {{k}_{\mathrm{c}}+ \left({1 -{k}_{11}}\right)}\right\rbrack \left\lbrack {{k}_{\mathrm{a}}+ \left({1 -{k}_{8}}\right)+ \left({1 -{k}_{9}}\right)}\right\rbrack +\\{k}_{\mathrm{b}}\left\lbrack {{k}_{\mathrm{c}}+ \left({1 -{k}_{11}}\right)+ {k}_{\mathrm{a}}+ \left({1 -{k}_{8}}\right)+ \left({1 -{k}_{9}}\right)}\right\rbrack $
where,
${k}_{\mathrm{a}}= \frac{\left({1 -{k}_{6}}\right)\left({1 -{k}_{10}}\right)}{\left({1 -{k}_{6}}\right)+ \left({1 -{k}_{7}}\right)+ \left({1 -{k}_{10}}\right)} $
${k}_{\mathrm{b}}= \frac{\left({1 -{k}_{6}}\right)\left({1 -{k}_{7}}\right)}{\left({1 -{k}_{6}}\right)+ \left({1 -{k}_{7}}\right)+ \left({1 -{k}_{10}}\right)} $
${k}_{\mathrm{c}}= \frac{\left({1 -{k}_{7}}\right)\left({1 -{k}_{10}}\right)}{\left({1 -{k}_{6}}\right)+ \left({1 -{k}_{7}}\right)+ \left({1 -{k}_{10}}\right)} $
The expressions for the pole voltages ${v}_{\mathrm{{yw}}}$ and ${v}_{\mathrm{{zw}}}$ are given by
$\left\{\begin{array}{l}{v}_{\mathrm{{yw}}}= {v}_{\mathrm{{yn}}}+ {v}_{\mathrm{{nw}}}\\{v}_{\mathrm{{zw}}}= {v}_{\mathrm{{zn}}}+ {v}_{\mathrm{{nw}}}\end{array}\right.$
The expression for the output voltage ${v}_{\mathrm{{yz}}}$ is given by
${v}_{\mathrm{{yz}}}= {v}_{\mathrm{{yw}}}- {v}_{\mathrm{{zw}}}$
The expression for the CMV ${v}_{\mathrm{{cm}}}$ is given by
${v}_{\mathrm{{cm}}}= \frac{{v}_{\mathrm{{yw}}}+ {v}_{\mathrm{{zw}}}}{2}$
From Fig. 1, the expression for ${v}_{\mathrm{{yg}}}$ in terms of ${v}_{\mathrm{{yw}}},{V}_{\mathrm{{PV}}}$ and ${v}_{\mathrm{{ug}}}$ is given by
${v}_{\mathrm{{yg}}}= {v}_{\mathrm{{yw}}}- {V}_{\mathrm{{PV}}}+ {v}_{\mathrm{{ug}}}$
Similarly, the expression for ${v}_{\mathrm{{zg}}}$ in terms of ${v}_{\mathrm{{zw}}},{V}_{\mathrm{{PV}}}$ and ${v}_{\mathrm{{ug}}}$ is given by
${v}_{\mathrm{{zg}}}= {v}_{\mathrm{{zw}}}- {V}_{\mathrm{{PV}}}+ {v}_{\mathrm{{ug}}}$
Adding (14) and (15) gives
${v}_{\mathrm{{yg}}}+ {v}_{\mathrm{{zg}}}= {v}_{\mathrm{{yw}}}+ {v}_{\mathrm{{zw}}}- 2{V}_{\mathrm{{PV}}}+ 2{v}_{\mathrm{{ug}}}$
The expression for ${v}_{\mathrm{{yg}}}$ and ${v}_{\mathrm{{zg}}}$ in terms of ${v}_{\mathrm{g}}$ is given by [20]-[21].
${v}_{\mathrm{{yg}}}+ {v}_{\mathrm{{zg}}}= {v}_{\mathrm{g}}$
Equating (16) and (17) gives
${v}_{\mathrm{{ug}}}= {0.5}{v}_{\mathrm{g}}+ {V}_{\mathrm{{PV}}}- {0.5}{v}_{\mathrm{{yw}}}- {0.5}{v}_{\mathrm{{zw}}}$
The analytical waveforms of pole voltages ${v}_{\mathrm{{yw}}}$ and ${v}_{\mathrm{{zw}}}$, output voltage ${v}_{\mathrm{{yz}}}$, terminal voltage ${v}_{\mathrm{{ug}}}$ and CMV ${v}_{\mathrm{{cm}}}$ are obtained using (3)-(13) and (18). The derived expressions are plotted using MATLAB software. The parameters used for obtaining the analytical waveforms are: VPN=400V, grid voltage vg=230V (RMS), grid frequency ${f}_{\mathrm{g}}= {50}\mathrm{{Hz}}$, and switching frequency ${f}_{\mathrm{{sw}}}= {500}\mathrm{\;{Hz}}$. Here, the switching frequency is taken very low to show the switching transitions in the pole voltages and output voltage clearly [20]-[21]. Fig. 6 shows the analytical waveforms of (a) pole voltage ${v}_{\mathrm{{yw}}}$,(b) pole voltage ${v}_{\mathrm{{zw}}}$,(c) output voltage ${v}_{\mathrm{{yz}}}$,(d) terminal voltage ${v}_{\mathrm{{ug}}}$ and (e) $\mathrm{{CMV}}{v}_{\mathrm{{cm}}}$ for the proposed five-level inverter. From Fig. 6(a) and (b), it can be observed that there are three levels $0,{V}_{\mathrm{{PV}}}/2$ and VPN in the pole voltages ${v}_{\mathrm{{yw}}}$ and ${v}_{\mathrm{{zw}}}$. From Fig. 6(c), it can be observed that there are five levels in the output voltage ${v}_{yz}$. For CCMV waveform shown in Fig. 6(e), the nature of terminal voltage waveform is purely low-frequency sinusoidal waveform with DC offset as shown in Fig. 6(d). The low frequency terminal voltage can be attributed to the constant value of CMV ${v}_{\mathrm{{cm}}}$ around 200V as can be observed from Fig. 6(e).
V. Simulation Results
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In order to validate the performance of the proposed five-level inverter simulation is done in MATLAB using the POWERSIM block sets. Table II presents the parameters that are considered for carrying simulation. Fig. 7 shows the simulation waveforms of the proposed five-level inverter. From Fig. 7(a), the output voltage ${v}_{\mathrm{{vz}}}$, having step waveform with transitions between 0 to VPN/2 and VPN/2 to VPN can be observed. This result in lower THD of the output voltage in the proposed topology when compared to the topology proposed in [20]-[21]. Fig. 7(b)-(e) show the waveforms of voltage across and the current through the switched capacitors ${C}_{\mathrm{S}1}$ and ${C}_{\mathrm{S}2}$. From Fig. 7(b) and (d), it can be observed that the switched capacitors ${C}_{\mathrm{S}1}$ and ${C}_{\mathrm{S}2}$ are charged to ${200}\mathrm{\;V}$ (i.e., half of the DC bus voltage VPN). The voltage ripple obtained from plots in Fig. 7(b) and (b) is around 3%. The currents ${i}_{\mathrm{{CS}}1}$ and ${i}_{\mathrm{{CS}}2}$ flowing through the switched capacitors ${C}_{\mathrm{S}1}$ and ${C}_{\mathrm{S}2}$ are shown in Fig. 7(c) and (e).
The RMS value of the current flowing through the capacitors is 7A. As said earlier, there is low voltage and current ripple in the switched capacitors ${C}_{\mathrm{S}1}$ and ${C}_{\mathrm{S}2}$. Fig. 7(f) shows the grid current waveform ${i}_{\mathrm{g}}$ having sinusoidal nature. Fig. 7(g) shows the terminal voltage waveform ${v}_{\mathrm{{yz}}}$. The terminal voltage ${v}_{\mathrm{{ug}}}$ is a low-frequency sinusoidal signal. The low frequency nature of terminal voltage results in high impedance of parasitic capacitance resulting in low value of leakage current ${i}_{\mathrm{{cpc}}}$ as shown in Fig. 7(h). The leakage current RMS value is around 0.02A. From Fig. 7(i), it can be observed that the value of CMV ${v}_{\mathrm{{cm}}}$ is maintained constant at around 200V for all the output voltage levels. The proposed topology can also be operated for a modulation indices less than or equal to 0.5 . Fig. 8 shows the simulation waveforms of the proposed system with the modulation index of 0.405 . The proposed inverter output voltage waveform for the given modulation index ${m}_{\mathrm{a}}$ equal to 0.405 is shown in Fig. 8(a).The output voltage of the proposed five-level inverter has three levels: $+{V}_{\mathrm{{PV}}}/2,0$ and -VPN/2.
Figs. 8(b) and (e) shows the voltage waveforms across the switched capacitors ${C}_{\mathrm{S}1}$ and ${C}_{\mathrm{S}2}$ for the given modulation index ${m}_{\mathrm{a}}$ equal to 0.405 . As the charging of the series connected switched capacitors ${C}_{\mathrm{S}1}$ and ${C}_{\mathrm{S}2}$ occurs during the 0 output voltage level, the switched capacitors ${C}_{\mathrm{S}1}$ and ${C}_{\mathrm{S}2}$ are able to generate the output voltage levels of $\pm {V}_{\mathrm{{PV}}}/2$. Thus, the proposed inverter even can be operated in the lower modulation index. Fig. 8(c) and (f) show the waveforms of the current flowing through the switched capacitors. The peak value of the ripple current is around 15.5A. Fig. 8(d) shows the CMV waveform of the of the proposed five-level inverter for a modulation index less than 0.5 . From the subplot, it can be observed even at the lower modulation index also, the CMV is clamped to VPN/2. Fig. 9 shows the waveforms of the zoomed view of voltage across the switched capacitor ${v}_{\mathrm{{CS}}1}$ and the switched capacitor current ${i}_{\mathrm{{CS}}1}$ for the five-level inverter topology proposed in [18] and proposed five-level inverter. The voltage ripple of switched capacitors used in the proposed topology is around 3%, whereas the voltage ripple of switched capacitors used in the topology proposed in [18] is around 6%.
Therefore, the proposed topology has less voltage ripple in the switched capacitor with less charging and discharging currents. In the five-level inverter proposed in [18], the capacitor is not charged for a period of 60° in each cycle of the output voltage. This results in high charging and discharging currents of the switched capacitors. However, the strategy of charging the switch capacitor in each switching cycle reduces magnitude of the charging and discharging currents through it.
Thus, the magnitude of the inrush current in the proposed configuration is minimum during operation and at starting can be minimized by using precharged capacitors. The peak value of currents in the switched capacitors is around 25A for the proposed five-level inverter. The peak value of switched capacitor current is around 50A for the five-level inverter proposed in [18]. The RMS value of currents in the switched capacitors is around 7A in the proposed five-level inverter. The RMS value of switched capacitor current is around 8.2A for the five-level inverter proposed in [18]. Due to high value of RMS current, ripple voltage across the capacitor and required capacity of switch capacitor is high in the five-level inverter proposed in [18] compared to the proposed five-level inverter topology.
Further, to compare the PV source utilization, the simulation is done for proposed configuration and configuration given in [18] under identical conditions. In the simulation intentionally, the low value of the PV buffer capacitor of ${1000\mu }\mathrm{F}$ is kept across the PV source. The simulation of both systems is done in identical conditions. Fig. 10(a)-(c) and (j)-(i) show the waveforms of the output voltage, current, and power of the PV source for the five-level inverter [18] and proposed inverter. The voltage ripple in the PV source is lower in the proposed system, as shown in Fig. 10(a) and (g). Further, the PV source operates near the open circuit voltage in [18], due to the long 60° (approximately 3.33ms) discharging period. The operation of the PV source at open circuit voltage can be verified by the zero PV current and power as shown in Fig. 10(b) and (c), respectively. Same is not true for the proposed configuration. PV power does not have zero value supporting effective utilization of the PV source when compared with another inverter [18]. Further, higher average PV source current and power values can also be verified. Thus, the proposed configuration utilizes the PV source more effectively in comparison to the configuration proposed in [18], as shown in Fig. 10(c) and (i). Fig.10(d)-(f) show the waveforms of output voltage ${v}_{\mathrm{{yz}}}$, grid current ${i}_{\mathrm{g}}$ and average output power of inverter ${P}_{\mathrm{O},\text{ Aveg }}$ of the five-level inverter [18] and proposed inverter. From Fig. 10(e), it can be observed that the average output power is less in the inverter [18] when compared to the proposed inverter.
A-Number of levels in the output voltage, B-Number of power semiconductor devices used, C-Number of independent PV sources required.
Further, the simulation was done to determine the efficiency of the proposed configuration. Fig. 11 shows the switching and conduction losses for all the switches employed in the proposed configuration. The proposed inverter is also compared with the other TPVI topologies with five-level output that exist in the literature. The efficiency plot for the proposed configuration along with other existing five-level TPVI is given in Fig. 12 for the power varying from 1000W to 2500W. A thorough examination of losses is conducted using PLECS software for all the topologies shown in Fig. 12. In this analysis, each topology is simulated for a system with approximately 2.5kW power and a frequency of 50Hz, operated at a switching frequency of 5kHz within the PLECS environment. The switch and diode models employed for loss analysis in PLECS are IGW30N60T_IGBT and IGW30N60T, respectively for all the topologies. From Fig. 12, it can be observed that the efficiency of the proposed inverter is approximately around 98% over wide range of output power. Also from the Fig.12, it can be observed that the proposed topology has better efficiency compared to the other existing five-level TPVI topologies. Table III shows the comparison of the proposed five-level inverter with other existing TPVI topologies. Since the proposed topology comes under the family of symmetrical inductor-based inverters, only such topologies are considered for comparison. The merits of the proposed five-level topologies can be observed in Table III.
VI. Experimental Results
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In order to further validate the proposed five-level inverter, an experimental prototype is developed. The parameters used for obtaining the experimental waveforms shown in Table IV. The programmable DC power supply were used instead of PV panels [20]-[21]. The pulses for the five-level inverter were generated using Basys 3 FPGA board. The MOSFETs IRF 640 were used as switches in the proposed five-level inverter. The driver IC HCPL 3120 is used to drive these switches. The output of the proposed five-level inverter is connected to a resistive load ${R}_{\text{load }}$ via an LC filter [20]-[21]. The photograph of the experimental setup is shown in Fig. 13. Fig. 14 shows the experimental of (a) output voltage ${v}_{\mathrm{{yz}}}$,(b) voltage ${v}_{\text{load }}$ across the resistive load, and current ${i}_{\text{load }}$ through the resistive load,(c) terminal voltage ${v}_{\mathrm{{ug}}}$,(d) leakage current ${i}_{\mathrm{{cpc}}}$,(e) CMV ${v}_{\mathrm{{cm}}}$,(f) voltage ${v}_{\mathrm{{CS}}1}$ across switched capacitor ${C}_{\mathrm{S}1}$ and current ${i}_{\mathrm{{CS}}1}$ through the switched capacitor ${C}_{\mathrm{S}1}$ for the proposed five-level inverter. Fig. 15 shows the experimental waveforms of (a) output voltage ${v}_{\mathrm{{yz}}}$ and (b) CMV ${v}_{\mathrm{{cm}}}$ of the proposed five-level inverter for modulation index less than 0.5 . The experimental waveforms obtained from the hardware setup exactly matches with the simulation results. This further justifies the operation of proposed five-level inverter. The experimental results were also taken in dynamic operating conditions like step change in the load, variable line frequency, step change in the input voltage. Fig. 16 shows the experimental waveforms of output voltage ${v}_{\mathrm{{yz}}}$, voltage across the load ${v}_{\text{load }}$, current flowing through the load ${i}_{\text{load }}$, terminal voltage ${v}_{\mathrm{{ug}}}$, leakage current ${i}_{\mathrm{{cpc}}},\mathrm{{CMV}}{v}_{\mathrm{{cm}}}$ and voltage across switched capacitor ${C}_{\mathrm{{Sl}}}{v}_{\mathrm{{CSl}}}$, current flowing through the switched capacitor ${C}_{\mathrm{{Sl}}}{i}_{\mathrm{{CSl}}}$ for the proposed five-level inverter with step change in the load ${R}_{\text{load }}$ from ${50\Omega }$ to ${100\Omega }$. Fig. 17 shows the experimental waveforms of output voltage ${v}_{\mathrm{{yz}}}$, voltage across the load ${v}_{\text{load }}$, current flowing through the load ${i}_{\text{load }}$, terminal voltage ${v}_{\mathrm{{ug}}}$, leakage current ${i}_{\mathrm{{cpc}}},\mathrm{{CMV}}{v}_{\mathrm{{cm}}}$ and voltage across switched capacitor ${C}_{\mathrm{{Sl}}}{v}_{\mathrm{{CSl}}}$, current flowing through the switched capacitor ${C}_{\mathrm{{Sl}}}{i}_{\mathrm{{CSl}}}$ for the proposed five-level inverter with variable line frequency ${f}_{\mathrm{g}}$ from 50Hz to 60Hz. Fig. 18 shows the shows the experimental waveforms of output voltage ${v}_{\mathrm{{vz}}}$, voltage across the load ${v}_{\text{load }}$, current flowing through the load ${i}_{\text{load }}$, terminal voltage ${v}_{\mathrm{{ug}}}$, leakage current ${i}_{\mathrm{{cpc}}}$, CMV ${v}_{\mathrm{{cm}}}$ and voltage across switched capacitor ${C}_{\mathrm{{Sl}}}{v}_{\mathrm{{CSl}}}$, current flowing through the switched capacitor ${C}_{\mathrm{{Sl}}}$ ${i}_{\mathrm{{CS}}1}$ for the proposed five-level inverter with step change in the input voltage VPN from 100V to 80V. During all these dynamic operating conditions, the proposed five-level inverter is operating successfully.
VII. Conclusion
Less
A five-level transformerless inverter for the alleviation of the leakage current in the PV systems by considering the effect of SDJC is proposed in this paper. The proposed topology generates five levels in the inverter output voltage by using two switched capacitors. The switched capacitors discharge for the voltage levels $\pm {V}_{\mathrm{{PV}}}/2$ and charges for the remaining voltage levels. The switched capacitors in the proposed topology have less charging and discharging currents. The switched capacitors in the five-level inverter also have low voltage and current ripples. The two switched capacitors used in the five-level inverter have self-charge balance feature. Due to subsequent charging and discharging in the switching periods, the size of switched capacitors used in the five-level inverter will be less. Also, the two switched capacitors used in the proposed five-level inverter are discharged in parallel. This results in the reduction of the switched capacitor value to half. The proposed five-level inverter also minimizes the ripple in the buffer capacitor of the PV panel. Further, the proposed five-level inverter effectively utilizes the PV source as the series connected switch capacitors, and the DC bus buffer capacitor across the PV source comes in parallel in each switching period. The proposed five-level also generate three levels in the output voltage for the lower modulation index. In addition to the above discussed, the proposed five-level inverter maintains CCMV by taking into account the effect of SDJC. This helps in alleviating the CMC and leakage current in the PV systems. As a result, the size of common mode chokes and EMI filters required at the output of five-level inverter may be minimized.
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Appendix
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Year 2024 volume 9 Issue 3
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Cite this Article
BibTeX
Article Info
doi: 10.24295/CPSSTPEA.2024.00010
  • Receive Date：2023-10-13
  • Online Date：2025-07-05
  • Published：2024-09-10
Article Data
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History
  • Received：2023-10-13
  • Revised：2024-04-24
  • Accepted：2024-05-25
Affiliations
    1 National Institute of Technology Raipur Department of Electrical Engineering Raipur 492010 India
    2 University of Technology Sydney Faculty of Engineering and Information Technology Sydney 2007 Australia
    3 Newcastle University Singapore 567739 Singapore

Corresponding:

Sachin Jain.
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表12种不同金属材料的力学参数
科
Family		 属数
Number of
genus		 种数
Number of
species		 占总种数比例
Percentage of
total species (%)		 属
Genus		 种数
Number of
species		 占总种数比例
Percentage of total
species (%)
鹅膏菌科Amanitaceae 2 11 5.26 鹅膏菌属 Amanita 10 4.78
小菇科 Mycenaceae 2 12 5.74 丝盖伞属 Inocybe 5 2.39
多孔菌科 Polyporaceae 8 14 6.70 蜡蘑属 Laccaria 5 2.39
红菇科 Russulaceae 3 23 11.00 小皮伞属 Marasmius 6 2.87
小菇属 Mycena 11 5.26
光柄菇属 Pluteus 5 2.39
红菇属 Russula 17 8.13
栓菌属 Trametes 5 2.39
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