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Dynamic Current Balancing for Paralleled SiC MOSFETs With Circuit Mismatches Considering Circulating Current in Drive Circuit
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Yang HE, Junming ZHANG, Shuai SHAO
CPSS Transactions on Power Electronics and Applications | 2024, 9(2) : 219 - 229
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CPSS Transactions on Power Electronics and Applications | 2024, 9(2): 219-229
• Papers •
Dynamic Current Balancing for Paralleled SiC MOSFETs With Circuit Mismatches Considering Circulating Current in Drive Circuit
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Yang HE, Junming ZHANG, Shuai SHAO
Affiliations
  • Zhejiang University College of Electrical Engineering Hangzhou 310027 China

    • Yang He received the B.S. degree in electrical engineering from the Huazhong University of Science and Technology, Wuhan, China, in 2019. He is currently working toward the Ph.D. degree in electrical engineering with the Zhejiang University, Hangzhou, China. His research interests include applications of wide bandgap power devices and parallel connection of SIC MOSFETS.

    Junming Zhang received the B.S., M.S., and Ph.D. degrees in electrical engineering from the Zhejiang University, Hangzhou, China, in 1996, 2000, and 2004, respectively. He is currently a Professor with the College of Electrical Engineering, Zhejiang University. From 2010 to 2011, he was a Visiting Scholar with the Department of Electrical and Computer Engineering, Michigan State University, East Lansing, MI, USA. His research interests include power electronics system integrations, power management, and high-efficiency converters. Prof. Zhang is an Associate Editor for the IEEE Transactions on Industry Applications and CPSS Transactions Power Electronics and Application.

    Shuai Shao received the B.S. degree in electrical engineering from the Zhejiang University, Hangzhou, China, in 2010, and the Ph.D. degree in electrical and electronic engineering from the University of Nottingham, Nottingham, U.K., in 2015. In 2015, he joined the College of Electrical Engineering, Zhejiang University, as a Lecturer. In January 2020, he was promoted as an Associate Professor. He has authored/coauthored more than 50 peer-reviewed journal and conference papers. His research interests include solid-state transformers, bidirectional dc-dc converters, and fault detection in power converters. Dr. Shao was a Guest Associate Editor for the IEEE Journal of Emerging and Selected Topics in Power Electronics and CES Transactions on Electrical Machines and Systems.

Published: 2024-06-10 doi: 10.24295/CPSSTPEA.2024.00004
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Parallel operation of silicon carbide (SiC) metaloxidesemiconductor fieldeffect transistors (MOSFETs) is necessary for highpower applications. However, the dynamic current sharing of paralleled devices is very sensitive to mismatched circuit parasitic inductances due to their high switching speeds. Symmetric parasitic inductances are usually difficult to realize because of the limitation of circuit layout, especially when more than two devices are paralleled. In this paper, the effects of the circulating current in the drive circuit caused by the circuit mismatches, which result in dynamic current imbalance, are firstly analyzed in detail. The influences of related drive circuit parameters are presented, which reveal the mechanism of dynamic current sharing. Motivated by the analysis, a suppression method of the circulating current is proposed by inserting additional impedances in the drive circuit. Considering the coupling noises introduced by the additional impedances, the concept of blocking unit is proposed to guarantee the proper operation of the drive circuit. A simple circuit implementation and the operation principle are presented. Finally, the drive method is validated by both simulations and experiments. Experimental results show the peak current imbalance is reduced from 16.5% to 3.2% and the maximum switching loss imbalance is reduced by half.

Circulating current  /  circuit mismatches  /  dynamic current sharing  /  gate driver  /  paralleled SiC MOSFETS.
Yang HE, Junming ZHANG, Shuai SHAO. Dynamic Current Balancing for Paralleled SiC MOSFETs With Circuit Mismatches Considering Circulating Current in Drive Circuit[J]. CPSS Transactions on Power Electronics and Applications, 2024 , 9 (2) : 219 -229 . DOI: 10.24295/CPSSTPEA.2024.00004
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I. Introduction
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WTTH the superior intrinsic material properties of silicon carbide (SiC), SiC metal-oxide-semiconductor field-effect transistor (MOSFET), which can operate at higher voltage, higher switching frequency and higher temperature, is a good replacement for the silicon (Si) power device in applications like solar inverters, railway traction inverters and electric vehicles [1],[2]. Limited by the material performance and low yield, the current ratings of single commercial SiC MOSFET chips are usually not large enough for high-power applications. Parallel operation of SiC MOSFETs is necessary to improve the capacity of power electronics systems [3],[4]. However, the current imbalance of paralleled SiC MOSFETs caused by mismatched device parameters and asymmetric circuit layout is still a problem to be solved [5]. Current imbalance will result in uneven junction temperatures and influence the reliability of the whole system. Therefore, it is necessary to investigate the mechanisms of current sharing and explore methods to balance the currents of paralleled devices.
To date, many research works on current sharing methods for paralleled devices have been carried out. The influences of device parameters on both static current sharing and dynamic current sharing are analyzed in [5]-[7]. The current imbalance caused by mismatched device parameters can be improved by advanced semiconductor process technology or device screening methods [8],[9]. The mismatched circuit parameters also play an important role in current sharing [5],[7],[10]-[14]. It is revealed that the power-source inductances are highly related with the dynamic current sharing of paralleled devices while other parts of parasitic inductances have minor effects.
In summary, the factors affecting current sharing can be categorized as device parameter tolerances and circuit parasitic mismatches. Therefore, the state-of-the-art current balancing methods are usually aimed at dealing with one or both of the factors. Among these methods, some active gate driver (AGD) methods and coupled inductor methods can mitigate the current imbalance caused by both types of factors, while circuit layout optimization methods usually focus on circuit parasitic mismatches.
The AGDs use the sensed current information to control the gate parameters of paralleled devices [15]-[19]. The advantage of the AGDs is the flexible control. However, complex analog/ digital systems are required to adjust the drive signal delay, drive voltage or drive current, which increase the cost and lower the reliability. Besides, there has been no satisfactory solution of a compact and high-bandwidth current detection circuit, which is usually necessary to AGDs. The $\mathrm{d}i/\mathrm{d}t$ based analog feedback circuits in [20] and [21] are simple and effective. However, it requires a symmetric circuit layout.
Coupled inductors are also commonly used to improve current sharing due to their simple structure [22]-[26]. However, it is difficult to improve the power density since the inductors are bulky. In [24]-[26], the inductor sizes are smaller due to their much lower inductances. Nevertheless, lower inductances also mean these methods are more sensitive to the circuit mismatches. These passive methods are also hard to be extended for more paralleled devices.
Considering the drawbacks of AGDs and passive methods, device screening methods are simpler and widely used in industry to eliminate the influences of device tolerances. Therefore, some recent research works focus on the circuit mismatches and the optimization of circuit layout. Identical equivalent power-source inductances can be achieved by the adjustments of lengths of current paths or additional current paths [27],[28]. The circuit mismatches are compensated by the common source inductances in [29]. Such methods are straightforward but may increase the equivalent parasitic inductances and decrease the switching speed. They are not suitable for applications require ultra-low parasitics. Additional capacitive components can change the transient current paths of the paralleled devices. DC decoupling capacitors or silicon-based capacitors are adopted in [30]-[33] to reduce the circuit mismatch. These methods do not require complex circuit layout and can achieve good current balance. However, the footprints of ceramic capacitors are still too large for a power module, while the capacitances of silicon-based capacitors are limited.
As discussed above, the combination of device screening and symmetric layout design is a practical way to improve current sharing. However, the layout flexibility might be limited, which will affect other aspects of circuit performance. As mentioned in [33], the root cause of dynamic current imbalance with circuit mismatches is the circulating current in the gate drive circuit. Therefore, the current imbalance might be suppressed by special drive circuit design. However, the mechanism of the circulating current in the drive circuit with circuit mismatches has not been fully revealed by now. Different drive topologies were compared in [34] but the key factors and in-depth current sharing analysis are missed. Meanwhile, there have been seldom research works about the drive circuit design considering mismatched parasitics. Common-mode choke was inserted in the gate drive loop to limit the current imbalance in [35]. This is a simple method but the choke is bulky, which is hard to be integrated.
In this paper, the influence of the circulating current is comprehensively analyzed based on the equivalent circulating current loop. The suppression method of the circulating current is presented considering potential coupling noises in the drive circuit. A drive method is proposed to limit the circulating current and improve dynamic current sharing based on the concept of blocking units. The circuit implementation of the blocking unit is not sole can be very simple. Compared with layout optimization, the power circuit layout is more flexible with this method. Besides, the drive circuit composed of semiconductor components is suitable for further integration and extension to any number of paralleled devices.
The rest of this paper is organized as follows. In Section II, the influence of the circulating current in the drive circuit and the related parameters are comprehensively analyzed considering mismatched power-source inductances. Section III introduces the circulating current suppression method considering the potential coupling noises. The hardware setup, simulations, and experiments are presented to validate the effectiveness of the proposed gate drive method in Section IV. Finally, a conclusion is summarized in Section V.
II. Influence of Circulating Current in Drive Circuit
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The parasitic inductances of paralleled SiC MOSFETs are usually not matched in multichip power modules or power converters due to the layout restrictions. The difference between the power-source inductances will cause significant dynamic current imbalance even with identical power devices [27]-[28]. This section focuses on how the circulating current caused by such circuit mismatches influences the dynamic current sharing of paralleled devices. The relationship between the circulating current and the gate drive circuit parameters will be discussed.
The schematic of a double pulse test (DPT) circuit of 2 paralleled SiC MOSFETs is shown in Fig. 1. The parameters in the circuit are listed in Table I. The detailed drive circuit is shown in Fig. 1(b). The drive currents are amplified by 2 buffers after the drive signal ${V}_{\mathrm{g}}$. This drive circuit can enlarge the drive capability and guarantee the consistency of the driver loops. In order to simplify the analysis, ${L}_{\mathrm{S}1}$ and ${L}_{\mathrm{S}2}$, the main causes of current imbalance, are considered to be different, while the other parameters of two devices are considered to be identical.
In Fig. 1, the voltage potentials of the source terminals of $\mathrm{Q}1$ and $\mathrm{Q}2\left({V}_{\mathrm{S}1}\right.$ and $\left.{V}_{\mathrm{S}2}\right)$ are different because of the difference between ${L}_{\mathrm{S}1}$ and (${L}_{\mathrm{S}1}$ is assumed to be higher in Fig. 1). As a consequence, a circulating current $\left({i}_{\text{cir }}\right)$ will flow through the gate drive circuit. The gate source voltages and the related dynamic current sharing are affected by ${i}_{\text{cir }}$. The MOSFET is modeled as a voltage controlled current source in the current rising/falling stage, which can be expressed as
${i}_{\mathrm{D}}= {g}_{\mathrm{{fs}}}\left({{v}_{\mathrm{{gs}}}- {V}_{\mathrm{{th}}}}\right)$
where ${g}_{\mathrm{{fs}}}$ is the transconductance, ${v}_{\mathrm{{gs}}}$ is the gate-source voltage, and ${V}_{\mathrm{{th}}}$ is the threshold voltage. ${g}_{\mathrm{{fs}}}$ is considered as a constant in this paper to simplify the analysis. In the following analysis, the drain currents of 2 paralleled MOSFETs are expressed in the form of
$\left\{\begin{array}{l}{i}_{\mathrm{D}1}= {i}_{\mathrm{D}0}+ {\Delta i}\\{i}_{\mathrm{D}2}= {i}_{\mathrm{D}0}- {\Delta i}\end{array}\right.$
Based on (1) and (2), the drain current variation ${\Delta i}$ can be expressed as
${\Delta i}= {g}_{\mathrm{{fs}}}\left({{v}_{\mathrm{{gsl}}}- {v}_{\mathrm{{gs}}2}}\right)/2 ={g}_{\mathrm{{fs}}}\Delta {v}_{\mathrm{{gs}}}/2 $
where $\Delta {v}_{\mathrm{{gs}}}$ is the gate-source voltage difference. According to Fig. $1,\Delta {v}_{\mathrm{{gs}}}$ caused by the circulating current is highly related with the gate drive circuit. Therefore, the effects of the drive circuit parameters should be systematically analyzed.
The equivalent circuit of the drive circuit in Fig. 1(b) is shown in Fig. 2(a). The parasitcs $\left({{R}_{\mathrm{c}},{L}_{\mathrm{c}}}\right)$ of the connections to the power supply are also included. The capacitors ${C}_{\mathrm{P}}$ and ${C}_{\mathrm{N}}$ are decoupling capacitors for the buffers shown in Fig. 1(b). The turn-on and turn-off drive current paths are distinguished by red and blue lines.
Fig. 2(a) can be further simplified as Fig. 2(b), where only the turn-on drive current paths are considered. The power supply voltages are shorted because they do not contribute to the current difference. Decoupling capacitors are also shorted due to their very low impedances in the switching transients.
In Fig. 2(b), according to Kirchhoff’s voltage law and current law (KVL & KCL), the following relationship is presented:
${i}_{\mathrm{D}1}\left( s\right){Z}_{\mathrm{S}1}+ \left({{Z}_{\mathrm{G}}+ {Z}_{\mathrm{c}}+ {Z}_{\mathrm{S}1}+ {Z}_{\mathrm{S}2}}\right){i}_{\text{cir }}\left( s\right)= {i}_{\mathrm{D}2}\left( s\right){Z}_{\mathrm{S}2}$
where
$\left\{\begin{array}{l}{Z}_{\mathrm{S}1}= s{L}_{\mathrm{S}1}\\{Z}_{\mathrm{S}2}= s{L}_{\mathrm{S}2}\\{Z}_{\mathrm{G}}= 2\left({1/s{C}_{\mathrm{{gs}}}+ {R}_{\mathrm{g}}+ s{L}_{\mathrm{g}}}\right)//\left({{R}_{\mathrm{k}}+ s{L}_{\mathrm{k}}}\right)\\{Z}_{\mathrm{s}}= 2\left({{R}_{\mathrm{s}}/3 + s{L}_{\mathrm{g}}/3}\right)\end{array}\right.$
In Fig. 2(b), circulating current $\left({k{i}_{\text{cir }}}\right)$ charges/discharges the gate-source capacitance of $\mathrm{Q}1/\mathrm{Q}2$, which leads to $\Delta {v}_{\mathrm{{gs}}}$. The factor $k$ is a current sharing factor, which is defined as
$ k\left( s\right)= \frac{{R}_{\mathrm{k}}+ s{L}_{\mathrm{k}}}{1/s{C}_{\mathrm{{gs}}}+ {R}_{\mathrm{g}}+ {R}_{\mathrm{k}}+ s\left({{L}_{\mathrm{g}}+ {L}_{\mathrm{k}}}\right)} $
The difference between the gate-source voltages of two devices can be expressed as
$\Delta {v}_{\mathrm{{gs}}}\left( s\right)= \frac{{2k}\left( s\right){i}_{\text{cir }}\left( s\right)}{s{C}_{\mathrm{{gs}}}}$
Combining (2)-(7), the following expression can be derived:
$\frac{\Delta i}{{i}_{\mathrm{D}0}}\left( s\right)= \frac{\left({Z}_{\mathrm{S}2}- {Z}_{\mathrm{S}1}\right)}{{Z}_{\mathrm{S}1}+ {Z}_{\mathrm{S}2}+ \frac{s{C}_{\mathrm{{gs}}}}{k\left( s\right){g}_{\mathrm{{fs}}}}\left({{Z}_{\mathrm{S}1}+ {Z}_{\mathrm{S}2}+ {Z}_{\mathrm{G}}+ {Z}_{\mathrm{c}}}\right)} $
(8) can reflect the degree of dynamic current imbalance caused by mismatched power-source inductances. For a constant ${L}_{\mathrm{S}2}- {L}_{\mathrm{S}1}$, the dynamic current imbalance can be mitigated by increasing the denominator of the left side of (8). The device-related parameters, including ${C}_{\mathrm{{gs}}}$ and ${g}_{\mathrm{{fs}}}$, are fixed once the SiC MOSFETs is determined. The current imbalance can be reduced by increasing ${Z}_{\mathrm{S}1}$ and ${Z}_{\mathrm{S}2}$ simultaneous. However, larger parasitic inductances, which will cause severer parasitic oscillation and drain-source voltage spike, should be avoided.
(8) also indicates that the current sharing is highly related with the parameter configuration of the driver loops. Previous research works have tried to limit the circulating current by inserting additional ${R}_{\mathrm{k}}$ or ${R}_{\mathrm{c}}\left\lbrack {34}\right\rbrack$,[36]. However, the effects of these parameters on the dynamic current sharing performance have not been revealed. The influences can be evaluated by (8) based on the device parameters $\left({{C}_{\mathrm{{gs}}}= {3349}\mathrm{{pF}},{g}_{\mathrm{{fs}}}= {27}\mathrm{\;S}}\right)$ of the SiC MOSFET C3M0032120K from Cree and a set of circuit parameters $\left({{R}_{\mathrm{g}}= {10\Omega },{R}_{\mathrm{k}}= 5\mathrm{\;m}\Omega,{L}_{\mathrm{g}}= {10}\mathrm{{nH}},{L}_{\mathrm{k}}= {10}\mathrm{{nH}}}\right.$, ${L}_{\mathrm{{Sl}}}= 5\mathrm{{nH}},{L}_{\mathrm{S}2}= {10}\mathrm{{nH}},{R}_{\mathrm{c}}= 5\mathrm{m}\Omega,{L}_{\mathrm{c}}= {10}\mathrm{{nH}}$). As is shown in Fig. 3, the amplitudes of (8) are calculated based on the original parameters and different ${R}_{\mathrm{k}},{R}_{\mathrm{c}}$ or ${R}_{\mathrm{g}}$.
According to Fig. 3, the increase of ${R}_{g}$ can improve the dynamic current sharing because it decreases the factor $k$ and prevents the circulating current from charging the ${C}_{\mathrm{{gs}}}$. However, the switching speed is highly related with ${R}_{\mathrm{g}}$. It is also clear that increasing ${R}_{\mathrm{k}}$ is not effective for the current imbalance caused by the circulating current. The root cause of this phenomenon is that larger ${R}_{\mathrm{k}}$ can only decrease the circulating current through the kelvin source branch, which in turn increases the factor $k$, the circulating current through ${C}_{\mathrm{{gs}}}$, and the related $\Delta {v}_{\mathrm{{gs}}}$. Meanwhile, ${R}_{\mathrm{k}}$ is located in the driver loop, which will also affect the switching speed like ${R}_{\mathrm{g}}$. In contrast, ${R}_{\mathrm{c}}$ is outside the driver loop and can mitigate the total circulating current, which prevents the voltage potential difference at the source terminals from charging ${C}_{\mathrm{{gs}}}$. Therefore, it is shown in Fig. 3 that larger ${R}_{\mathrm{c}}$ can help improve the dynamic current sharing.
As discussed above, with the drive circuit configuration shown in Fig. 2, the circulating current in the drive circuit and the dynamic current imbalance can be decreased by inserting additional resistances in the connection paths of the power supply. However, whether the increase in the resistance will affect other performances of the drive circuit should be further analyzed.
III. Suppression Method of Circulating Current
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The effects of circulating current in the drive circuit and related parameters have been comprehensively analyzed in Section II. It is possible that the circulating current can be suppressed by additional impedance in the drive circuit. In order to guarantee the proper operation of the drive circuit, the influences of the additional impedance on circuit performance will be analyzed in this section. Meanwhile, a circulating current suppression method is introduced to improve the dynamic current sharing performance based on the analysis.
A. Influences of Additional Impedance
Due to the buffer stages and their decoupling capacitors in the circuitry shown in Fig. 1(b), additional impedances ${R}_{\mathrm{c}}$ inserted in the power supply paths will not affect the rising/ falling time of the switching transient. However, there are still problems for this circuit configuration.
The drive circuit in the turn-on transient is shown in Fig. 4. A totem-pole stage is usually used as the buffer. For simplicity, the drive circuit of $\mathrm{Q}1$ is not shown, which is similar to that of $\mathrm{Q}2$. The effect of additional resistances ${R}_{\mathrm{c}}$ is considered while other circuit parasitics are not shown for simplicity. As discussed in Section II, ${R}_{\mathrm{c}}$ should be large enough to suppress the circulating current, which means the source voltage difference $\left({{V}_{\mathrm{S}1}- {V}_{\mathrm{S}2}}\right)$ in the turn-on transient mainly drops across ${R}_{\mathrm{c}}$, as shown in Fig. 4. The circulating current and its effects are highlighted in blue. The base voltage ${V}_{\mathrm{b}}$ of the totem-pole stage (i.e. input drive signal of the buffer stage) is affected by this voltage spike. In Fig. 4, the green loop is the KVL loop for the input voltage $\left({V}_{\mathrm{b}}\right)$ of the totem-pole stage while the red loop represents the drive loop for the SiC MOSFET in the turn-on transient. The output voltage ${V}_{\mathrm{G}}$ of the buffer follows ${V}_{\mathrm{b}}$, which means there is a coupling noise at the output caused by the additional ${R}_{\mathrm{c}}$. Therefore, the gate-source voltages $\left({{v}_{\mathrm{{gs}}1},{v}_{\mathrm{{gs}}2}}\right)$ of two paralleled devices are also affected by the source voltage difference. The circuit shown in Fig. 4 fails to suppress the current imbalance even with additional ${R}_{\mathrm{c}}$. The circulating current is still suppressed by ${R}_{\mathrm{c}}$ but the proper operation of the drive circuit is affected. The totem stages are considered as switches fully turned on in Fig. 2, so the effect of the coupling noise caused by the additional resistances ${R}_{\mathrm{c}}$ is missed in the analysis of Section II.
B. Drive Circuit With Blocking Units
As discussed above, additional impedances in the drive circuit can suppress the circulating current but it will distort the gate drive signal because of the coupling noise. In order to eliminate the influence of the noise, a gate drive architecture is proposed and shown in Fig. 5. Additional blocking units are inserted before the drive current buffers, which provide the additional impedances required to suppress the circulating current.
The key effect of the blocking unit is to simultaneously transmit the driver signal to the floating gate-source capacitance of each device and block the source-to-source voltage ${V}_{\mathrm{{SS}}}$. The voltage ${V}_{\mathrm{g}}$ is the drive signal for the two blocking units. The outputs are the separate drive voltages $\left({{V}_{\mathrm{{gl}}},{V}_{\mathrm{g}2}}\right)$ for two drive current buffers. In the circuit, PGND1 and PGND2 connected to the kelvin sources of paralleled devices are floating, whose potentials can be higher or lower than the reference ground AGND of gate driver input side. The blocking units will withstand the source voltage difference ${V}_{\mathrm{{SS}}}$ induced by mismatched power-source inductances and limit the circulating current through the gate network. As long as the delay of two blocking units is matched, the drive circuit can mitigate the dynamic current imbalance caused by mismatched source inductances.
C. Circuit Implementation
The function of blocking unit might be realized by various circuits, such as isolators or level shifters. However, there has been no commercially available IC for this application. To achieve a simple circuit structure with discrete transistors, the circuit implementation of the blocking unit is composed of complementary MOSFETs and additional resistors in this paper, as shown in Fig. 6. Compared with the drive circuit shown in Fig. 4, only two extra MOSFETs are required.
In Fig. $6,{\mathrm{\;V}}_{\mathrm{{CC}}},{\mathrm{\;V}}_{\mathrm{{EE}}}$ and AGND represent the positive voltage, negative voltage, and ground of power supply, respectively. Each paralleled MOSFET Qn ( $n$ means the ${n}^{\text{th }}$ paralleled device) is configured with its own blocking unit. ${\mathrm{V}}_{\mathrm{{CC}}n}$ and ${\mathrm{V}}_{\mathrm{{EE}}n}$ are the positive voltage and negative voltage powering the buffers, which are held by the capacitors ${C}_{\mathrm{P}n}$ and ${C}_{\mathrm{N}n}$ and provide the drive current for the SiC MOSFET. PGND $n$ is connected to the kelvin source of the ${n}^{\text{th }}$ device, which is also the reference ground of the buffers. The additional impedance in Fig. 5 is realized by blocking connection resistors ${R}_{\mathrm{c}}$ between the power supply and the buffers, which limit the circulating current that charges ${C}_{\mathrm{{gs}}}$ and results in current imbalance.
Similar to the circuit shown in Fig. 4, the amplitude of input signal ${V}_{\mathrm{g}}$ will be affected by the voltage drops on ${R}_{\mathrm{c}}$ caused by ${V}_{\mathrm{{SS}}}$ in the switching transients as shown in Fig. 5. The complementary MOSFETs ${\mathrm{M}}_{\mathrm{P}n}$ and ${\mathrm{M}}_{\mathrm{N}n}$ is used to eliminate the influences of the voltage drop across ${R}_{\mathrm{c}}$, and shape the input signal ${V}_{\mathrm{g}}$ to a non-distorted pulse signal for the cascaded buffer stage. Two branches composed of Zener diodes $\left({{\mathrm{D}}_{\mathrm{{ZP}}n},{\mathrm{D}}_{\mathrm{{ZN}}n}}\right)$ and diodes $\left({{\mathrm{D}}_{\mathrm{P}n},{\mathrm{D}}_{\mathrm{N}n}}\right)$ are paralleled to ${R}_{\mathrm{c}}$ in order to protect ${\mathrm{M}}_{\mathrm{P}n}$ and ${\mathrm{M}}_{\mathrm{N}n}$ from false turning on or turning off during the transient. The fast switching of the small-signal transistors can help avoid the delay difference.
The operation principle of the circuit shown in Fig. 6 during the turn-on/off transient is briefly illustrated by the waveforms shown in Fig. 7. In Fig. 7, the blue line is the gate-source voltage of ${\mathrm{M}}_{\mathrm{N}n}$ and orange line is the voltage between the base of ${\mathrm{T}}_{\mathrm{N}n}$ and PGND $n$. When turning on the SiC MOSFET, ${\mathrm{M}}_{\mathrm{N}n}$ is turned off by ${V}_{\mathrm{{gs}}}\left({\mathrm{M}}_{\mathrm{N}n}\right)$ as shown in Fig. 7(a). There will be a spike of ${V}_{\mathrm{{gs}}}\left({\mathrm{M}}_{\mathrm{N}n}\right)$ after ${\mathrm{M}}_{\mathrm{N}n}$ is turned off, which is caused by the voltage drops on ${R}_{\mathrm{c}}$. The polarity and amplitude of this spike is dependent on the mismatched power-source inductances. Fig. 7 shows an example where the spike is positive. If the voltage difference between the power sources of the paralleled devices are too large, ${V}_{\mathrm{{gs}}}\left({\mathrm{M}}_{\mathrm{N}n}\right)$ might exceed the threshold voltage of ${\mathrm{M}}_{\mathrm{N}n}$ due to the spike, which will false turn on ${\mathrm{M}}_{\mathrm{N}n}$. Therefore, ${\mathrm{D}}_{\mathrm{{ZN}}n}$ is added to clamp the spike to ${V}_{\text{Zener }}$, which should be lower than ${V}_{\mathrm{{th}}}\left({\mathrm{M}}_{\mathrm{N}n}\right)$. This situation is shown in Fig. 7(a) by the red dot line. After turning off ${\mathrm{M}}_{\mathrm{N}n},{V}_{\mathrm{b}}\left({\mathrm{T}}_{\mathrm{N}n}\right)$ changes from ${\mathrm{V}}_{\mathrm{{EE}}n}$ to ${\mathrm{V}}_{\mathrm{{CC}}n}$, which turns on the SiC MOSFET. The high level of ${V}_{\mathrm{b}}\left({\mathrm{T}}_{\mathrm{N}n}\right)$ is smooth and not affected by the voltage drops on ${R}_{\mathrm{c}}$. The process of turn-off transient is shown in Fig. 7(b), which is similar to the turn-on process and not repeated here.
With discrete transistors ${M}_{P}$ and ${M}_{N}$, there might be a large overlapping range for the MOSFETs are turned on simultaneously. In order to avoid the potential overcurrent phenomenon and reduce the loss, resistors can be added in series with the MOSFETs to limit the current, as shown in Fig. 8, where the Zener diode branches are omitted. The resistors ${R}_{\mathrm{{limH}}}$ and ${R}_{\mathrm{{limL}}}$ can limit the current through the MOSFETs in the overlapping drive voltage range. The switching speed might be slightly reduced by the current limit resistances. To achieve a larger resistance and maintain a proper switching speed, as illustrated by the red and blue arrows in Fig. 8, ${R}_{\mathrm{{limH}}}$ and ${R}_{\mathrm{{limL}}}$ are added in the turn-on drive path and turn-off drive path, respectively. As a consequence, ${R}_{\text{limH }}$ only affects the turn-on speed while ${R}_{\text{limL }}$ only affects the turn-off speed.
The basic operation of the drive circuit with additional blocking unit is similar to that of the circuit shown in Fig. 4. With the current limit resistors, the power losses of the complementary is quite low, which hardly limit the switching frequency. The resistances will not influence the drive loss. The switching delay might be increased because the switching speeds of ${\mathrm{M}}_{\mathrm{P}n}$ and ${\mathrm{M}}_{\mathrm{N}n}$ are affected by the resistance of ${R}_{\mathrm{c}}$. The relationship between the dynamic current imbalance and the resistance of ${R}_{\mathrm{c}}$ can be analyzed by the same method demonstrated in Section II, which can guide the determination of resistance ${R}_{\mathrm{c}}$ according to given circuit parameters.
IV. Experimental Validation
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In this section, a DPT hardware platform is built to verify the proposed circulating current suppression method. The dynamic current sharing performance of paralleled SiC MOSFETs are evaluated by both simulation and experiments.
A. Layout of Power Circuit Loop
The equivalent circuit and the printed circuit board (PCB) layout of the DPT circuit are shown in Fig. 9. For simplicity, only power devices, the parasitics, and mutual couplings are shown in Fig. 9(a) and the high side devices are replaced by freewheeling diodes. Flux cancellation is adopted to minimize the parasitic inductance, which is realized by the opposite directions of device currents as marked in Fig. 9(b), like a busbar structure. Two decoupling capacitors $\left({C}_{\text{decl }}\right.$ and $\left.{C}_{\mathrm{{dec}}2}\right)$ are placed at both sides of the paralleled devices, which are used to achieve a more symmetrical power circuit loop as demonstrated in Fig. 9(a) by loops in different colors.
The layout of PCB is modeled and simulated at 30MHz by Ansys Q3D to extract the values of parasitic inductances. Considering the effects of mutual inductances, the equivalent key parasitic inductances in the commutation loops of low side devices are listed in Table II. It is found in Table II that the differences of equivalent parasitic inductances are still around $1 \sim 2\mathrm{{nH}}$ though efforts have been made to minimize the parasitic circuit mismatches, which means dynamic current imbalance will occur due to mismatched power-source inductances.
B. Parameter Design
The blocking resistance ${R}_{\mathrm{c}}$ in the blocking unit is important to the dynamic current sharing performance. In Section II, the relationship between dynamic current imbalance and various parameters has been demonstrated based on theoretical analysis. Though the coupling noise introduced by ${R}_{\mathrm{c}}$ is highlighted in Section III, the equivalent circuit of the drive circuit with blocking units is the same with that shown in Fig. 2, considering that the influence of the noise has already been eliminated. Therefore, the parameter ${R}_{\mathrm{c}}$ can be determined according to (8). Based on the extraction of parasitics, ${L}_{\mathrm{S}1}$ and ${L}_{\mathrm{S}2}$ (including the parasitics of package) are respectively set as ${5.5}\mathrm{{nH}}$ and ${7.5}\mathrm{{nH}}$, respectively. The gate resistance ${R}_{\mathrm{g}}$ is set as ${20\Omega }$ while other related parameters are the same as those used in the calculation of Fig. 3. The comparison of dynamic current sharing performance with different ${R}_{\mathrm{c}}$ is shown in Fig. 10. Fig. 10 shows the relationship in the frequency domain rather than the time domain. However, it is reasonable to approximately evaluate the dynamic current sharing based on the bandwidth of the rising/falling edge of the device current. The high frequency bandwidth (BW) of the rising edge of the current can be expressed as
$\mathrm{{BW}}= \frac{0.35}{{t}_{\mathrm{r}}}$
where ${t}_{\mathrm{r}}$ is the rising time of the dynamic current of the SiC MOSFET.
Assuming that ${t}_{\mathrm{r}}$ is ${40}\mathrm{{ns}},\mathrm{{BW}}$ is about ${8.75}\mathrm{{MHz}}$ according to (9). It can be seen that the magnitude of current imbalance is below 5% within the BW of the dynamic current when ${R}_{\mathrm{c}}$ is chosen to be 24 $\Omega$. Since the s-domain relationship cannot reflect the accurate relationship in the time domain, the design procedure above just gives an approximate range for ${R}_{\mathrm{c}}$. The effect of ${R}_{\mathrm{c}}$ can be further confirmed with the aid of circuit simulations.
C. Circuit Simulation
The power circuit for Pspice simulation is exactly the circuit shown in Fig. 9(a). Considering the symmetry of the layout, only two MOSFETs (Q1 & Q2) are considered in the simulations to avoid convergence problems. The parasitics are the same as the results extracted by Q3D. ${C}_{\text{dec 1 }}$ is composed of two ${100}\mathrm{{nF}}$ decoupling capacitors. The ESL of a single decoupling capacitor is set as 2nH. Two ${220\mu }\mathrm{F}$ capacitors with 50 nH ESL are connected in series to serve as the dc bus capacitance. In the simulations, high side freewheeling diodes are replaced by SiC Schottky barrier diodes (SBDs). The low side switches are SiC MOSFETs. The spice models of SBD C3D30065D and SiC MOSFET C3M0032120K provided by Cree are adopted in the simulations. The dc bus voltage is 400V.
The drive circuit includes two blocking units shown in Fig. 6. The gate resistance ${R}_{\mathrm{g}}$ is ${20\Omega }.{C}_{\mathrm{P}}$ and ${C}_{\mathrm{N}}$ are both ${10\mu }\mathrm{F}$. The spice models of Si MOSFETs DMP610DL and DMN67D7L from Diodes are used as ${\mathrm{M}}_{{\mathrm{P}}_{n}}$ and ${\mathrm{M}}_{{\mathrm{N}}_{n}}$ as shown in Fig. 6. The spice model of the buffer composed of ${\mathrm{T}}_{\mathrm{P}n}$ and ${\mathrm{T}}_{\mathrm{N}n}$ is ZXG-D3003E6 from Diodes.
The simulation results of the proposed drive method (Rc=24Ω) are compared with those of conventional drive circuit without blocking units and additional Rc, which are shown in Fig. 11. For the conventional drive circuit, the gate-source voltage is affected by the circulating current through the drive circuit, which results in dynamic current imbalance. The simulation results indicate that the influence of mismatched parasitics on the dynamic current sharing in the turn-off transient is less significant compared with that at turn-on transient. The device currents fall to zero fast before the gate-source voltages are affected by the circulating current. For the proposed drive method, the gate-source voltage difference is very small since the circulating current is limited by the additional impedances. Therefore, the dynamic current imbalance is also negligible.
The magnitudes total circulating current through the gate drive circuit in the switching transients in two different cases are also compared in the simulation, as shown in Fig. 12. It is clear that the circulating current can be effectively suppressed in both turn-on and turn-off transients by the proposed drive circuit. In the proposed drive circuit, it can be seen that the circulating current can also be quickly damped due to the existence of additional ${R}_{\mathrm{c}}$.
Corresponding to the theoretical waveforms shown in Fig. 7(a), the gate-source voltages of ${\mathrm{M}}_{\mathrm{N}1}$ and ${\mathrm{M}}_{\mathrm{N}2}$ and the base voltages of ${\mathrm{T}}_{\mathrm{N}1}$ and ${\mathrm{T}}_{\mathrm{N}2}$ in the turn-on transient are shown in Fig. 13. It is shown that the gate-source voltages of the MOSFETs in the blocking units are affected because of the voltage drop on ${R}_{\mathrm{c}}$. However, the input voltages of the BJT buffers are not affected. Therefore, the drive voltage can be transmitted to the gates of SiC MOSFETs without coupling noises.
D. Hardware Setup
The hardware setup is shown in Fig. 14. The part numbers of the key components are listed in Table III. The device currents are measured by Rogowski coils from PEM (30 MHz, 300 A). The load inductance is composed of two ${50\mu }\mathrm{H}$ air-core inductors in series. The bus voltage is ${400}\mathrm{\;V}$ in the following experimental results. Fig. 14(b) shows the PCB of the drive circuit. The parameters are the same as those used in the circuit simulations.
The SiC MOSFETs with similar transfer characteristics are screened in advance. The transfer curves are measured by the curve tracer Keysight B1505A at 20V drain-source voltage, which are shown in Fig. 15.
E. Experimental Results
According to Fig. 6, the gate driver is equivalent to a conventional drive circuit when Rc=0. Therefore, current sharing performances are tested under 2 different conditions Rc=0, and (Rc=24Ω) to compare the effects of the gate drivers. The experimental results are shown in Fig. 16 and Fig. 17.
As is shown in Fig. 9, the physical positions of Q1 and Q4 is symmetrical. Therefore, the current of Q1 is close to that of Q4 in tests. The relationship between Q2 and Q3 is also similar. According to the theoretical analysis and simulation, the power-source inductances of $\mathrm{Q}1$ and $\mathrm{Q}4$ are lower, which results in higher device currents in the turn-on transient when ${R}_{\mathrm{c}}= 0$. When the resistance of ${R}_{\mathrm{c}}$ gets larger, the dynamic current imbalances in the turn-on transient become lower, which validates the effectiveness of the proposed gate drive method. The maximum turn-on current imbalances are summarized in Table IV. The maximum current imbalance is reduced from ${6.7}\mathrm{\;A}$ to ${1.3}\mathrm{\;A}$ when ${R}_{\mathrm{c}}$ is increased to ${24\Omega }$. The ratio of maximum current imbalance to average device current is reduced from 16.5% to only 3.2%. In Fig. 16 and Fig. 17, the waveforms of gate-source voltages are nearly the same, which seems to be unreasonable. However, considering ${g}_{\mathrm{{fs}}}$ of the SiC MOSFET is ${27}\mathrm{\;S}$, the maximum dynamic current imbalance can reach $7\mathrm{\;A}$ when $\Delta {v}_{\mathrm{{gs}}}$ is around only ${250}\mathrm{{mV}}$, which is too low to be observed in the experimental waveforms. The initial current before the turn-off transient is dependent on static current sharing, which might also influence the dynamic current sharing. Meanwhile, the current slew rate is relatively larger in the turn-off transient. Therefore, current balancing effect during the turn-off transient is less obvious. The total switching losses of the paralleled devices are calculated and listed in Table V. The ratio of maximum switching loss imbalance to the average switching loss is reduced from 11.1% to ${5.3}\%$ when ${R}_{\mathrm{c}}$ increases from 0 to ${24\Omega }$. Generally, the experimental results are consistent with the simulation results.
The gate-source voltages of ${\mathrm{M}}_{\mathrm{N}1}$ and ${\mathrm{M}}_{\mathrm{N}2}$ in the blocking units are shown in Fig. 18. The voltage spikes are similar to the simulation waveforms shown in Fig. 13. Since efforts are taken to minimized the power-source inductances mismatch, the magnitudes of voltage spikes are very low, which are only around $1\mathrm{\;V}$ and far below the threshold voltage of ${\mathrm{M}}_{\mathrm{N}n}$. Therefore, there is enough margin for the proposed gate driver to operate with a larger power-source inductance mismatch or a higher current slew rate.
V. Conclusion
Less
This paper presents a gate drive method to suppress the circulating current in the drive circuit of paralleled SiC MOS-FETs with circuit parasitic mismatches, which can improve the dynamic current sharing. The influence of the circulating current on the dynamic current sharing, which has not been fully analyzed by previous works, is elaborated based on a theoretical analysis. The analysis reveals the effects of related circuit parameters and potential circulating suppression method. To limit the circulating current, additional impedances are required in the circulating current loop, which will introduce coupling noises and interfere the proper operation of the drive circuit. The concept of blocking unit is introduced to eliminate the influences of coupling noises. The circuit implementation of the blocking unit is flexible and can be realized by a simple circuit using several transistors. Therefore, it is easy to be integrated. The method also features with good extensibility, which is applicable to any number of paralleled devices.
Funding
Less
  • National Key Research and Development Program of China(2021YFB2401600)
  • Eaton Corporation
References
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Appendix
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Year 2024 volume 9 Issue 2
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Cite this Article
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Article Info
doi: 10.24295/CPSSTPEA.2024.00004
  • Receive Date：2023-12-17
  • Online Date：2025-07-05
  • Published：2024-06-10
Article Data
Affiliations
History
  • Received：2023-12-17
  • Revised：2024-01-30
  • Accepted：2024-03-01
Funding
National Key Research and Development Program of China(2021YFB2401600)
Eaton Corporation
Affiliations
    Zhejiang University College of Electrical Engineering Hangzhou 310027 China

Corresponding:

Junming Zhang.
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表12种不同金属材料的力学参数
科
Family		 属数
Number of
genus		 种数
Number of
species		 占总种数比例
Percentage of
total species (%)		 属
Genus		 种数
Number of
species		 占总种数比例
Percentage of total
species (%)
鹅膏菌科Amanitaceae 2 11 5.26 鹅膏菌属 Amanita 10 4.78
小菇科 Mycenaceae 2 12 5.74 丝盖伞属 Inocybe 5 2.39
多孔菌科 Polyporaceae 8 14 6.70 蜡蘑属 Laccaria 5 2.39
红菇科 Russulaceae 3 23 11.00 小皮伞属 Marasmius 6 2.87
小菇属 Mycena 11 5.26
光柄菇属 Pluteus 5 2.39
红菇属 Russula 17 8.13
栓菌属 Trametes 5 2.39
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