Home Journals Articles Updates About
CN
image
收藏切换
High-Resolution Digital PWM Optimization Method for Critical Path Delay in General FPGA
收藏切换
PDF
Bailong XU, Qianming XU, Peng GUO, Yingzhe JIA, Yandong CHEN, An LUO
CPSS Transactions on Power Electronics and Applications | 2024, 9(2) : 190 - 206
Less
收藏切换
CPSS Transactions on Power Electronics and Applications | 2024, 9(2): 190-206
• Papers •
High-Resolution Digital PWM Optimization Method for Critical Path Delay in General FPGA
Full
Bailong XU, Qianming XU, Peng GUO, Yingzhe JIA, Yandong CHEN, An LUO
Affiliations
  • Hunan University College of Electrical and Information Engineering Changsha 410082 China

    • BaiLong Xu was born in Anhui, China, in 1992. He received the B.S. degree in Electrical Engineering from the Harbin Engineering University, Harbin, China, in 2014, and M.S. degree in Electrical Engineering from the School of Electrical and Electronic Engineering, Huazhong University of Science and Technology, Wuhan, China, in 2017. In the field of electric vehicles, he worked as a hardware engineer from 2017 to 2021. Now, for a doctorate, he is studying electrical engineering at Hunan University, Changsha, China. His research interests include High power density DC/DC converters, Multi-port converters, and their control technology.

    Qianming Xu was born in Henan, China, in 1989. He received the B.S. degree in electrical engineering and automation and the Ph.D. degree in electrical engineering from Hunan University, Changsha, China, in 2012 and 2017, respectively. Since 2023, he has been a Professor with the College of Electrical and Information Engineering, Hunan University, Changsha, China. His research interests include a multilevel converter, power electronic reliability monitoring, and power quality control.

    Peng Guo was born in Hunan, China, in 1992. He received the B.S. degree in electrical engineering from the Wuhan University of Technology, Wuhan, China, in 2015, and the Ph.D. degree in electrical engineering from Hunan University, Changsha, China, in 2020. He was an Associate Professor in Hunan University, China. His main research interests include a modular multilevel converter, switch-mode power amplifier, and model predictive control.

    Yingzhe Jia received the B.E. degree in electrical engineering from Shandong University, China, in 2015, and the Ph.D. degree in electrical and electronic engineering from the University of Manchester, Manchester, U.K. in 2020. He is currently a research associate with the college of Electrical and Information Engineering, Hunan University, China. His research interests include stability analysis of power electronics-based generations, harmonics analysis, operations in power systems, etc.

    Yandong Chen was born in Hunan, China, in 1979. He received the B.S. and M.S. degrees in instrument science and technology and the Ph.D. degree in electrical engineering from Hunan University, Changsha, China, in 2003, 2006, and 2014, respectively. He was a Professor with the College of Electrical and Information Engineering, Hunan University. His research interests include power electronics for microgrid, distributed generation, power quality, and energy storage. He is a recipient of the 2014 National Technological Invention Awards of China, and the 2014 WIPO-SIPO Award for Chinese Outstanding Patented Invention. He is a member of IEEE Power Electronics Society.

    An Luo was born in Changsha, China, in 1957. He received the B.S. and M.S. degrees in industrial automation from Hunan University, Changsha, in 1982 and 1986, respectively, and the Ph.D. degree in fluid power transmission and control from Zhejiang University, Hangzhou, China, in 1993. Between 1996 and 2002, he was a Professor at Central South University. Since 2003, he has been a Professor in the College of Electrical and Information Engineering, Hunan University, where he also serves as the Chief of the National Electric Power Conversion and Control Engineering Technology Research Center. His research interests mainly include distributed generation, microgrid, and power quality. He was elected to the Chinese National Academy of Engineering (CNAE) in 2015, the highest honor for scientists and engineers and scientists in China. He has won the highly prestigious China National Science and Technology Awards three times (2014, 2010, and 2006).

Published: 2024-06-10 doi: 10.24295/CPSSTPEA.2024.00003
Outline
收藏切换

This paper proposes a highresolution digital pulse width modulator (DPWM) signal optimization method for the critical path delay based on a field programmable gate array (FPGA), which mainly aims to improve the output regulation accuracy and linearity of the DPWM. This method realizes highresolution and highlinearity DPWM output by constructing the logical symmetric multiplexer and the synchronous 2to1 selector for the critical path, and a simple placement constraint is used to reduce the critical path delay deviation. The highresolution DPWM signal has the advantages of excellent linearity, easy expansion, and strong versatility, thus especially suitable for power electronic switching converters with high frequency, high accuracy, and high realtime control. The simulation and experimental results show that the DPWM with different FPGA achieves a resolution of 312.5 ps and high linearity, where R2 is up to 0.99999. Finally, the proposed method is verified in a 48 V to 1 V DC/DC converter with a switching frequency of 1 MHz.

DPWM  /  FPGA  /  high-linearity  /  high-resolution
Bailong XU, Qianming XU, Peng GUO, Yingzhe JIA, Yandong CHEN, An LUO. High-Resolution Digital PWM Optimization Method for Critical Path Delay in General FPGA[J]. CPSS Transactions on Power Electronics and Applications, 2024 , 9 (2) : 190 -206 . DOI: 10.24295/CPSSTPEA.2024.00003
Full Text
Less
I. Introduction
Less
SWITCHING converters have been used more and more widely due to their advantages of flexible control, small size, and high efficiency. The volume and weight of the switching converter can be reduced with the increase of the switching frequency. With the rapid development of soft switching and semiconductor technology, switching converters can still achieve high-efficiency operation at switching frequencies up to MHz. In addition, the dynamic characteristics of switching converters are significantly improved at higher switching frequencies. Digital control technology has been widely used in high-frequency switching converters due to its reliability, strong scalability, and flexible control. For example, the control loop does not need complex analog components for feedback control. It is all completed by a highly integrated microprocessor with a simple structure and high reliability. The controller can easily extend complex nonlinear control algorithms to improve the steady-state and dynamic performance of the converter. By modifying the software code of the controller and reprogramming, the control method update of the converter can be completed without modifying the hardware. The control system of the digital switching converter mainly consists of an analog-to-digital converter (ADC), a digital compensator, and a digital pulse width modulator (DPWM), as shown in Fig. 1. The higher resolution of ADC and DPWM, the higher control accuracy of the converter output voltage can be obtained. At the same time, the resolution of the DPWM signal needs to be higher than that of the ADC to reduce the output voltage error and avoid limit cycle oscillation [1]-[3]. As described in Fig. 2, the desired output voltage ${V}_{\mathrm{O}}$ is within the range of ${V}_{\mathrm{{AD}}}$, and the value after ADC quantization is ${E0}$. When the DPWM resolution is low, the quantized value of the output voltage ${V}_{\mathrm{L}}$ is ${E1}$ or ${E2}$, which cannot reach ${E0}$. At this time, the control loop will continuously perform feedback adjustment, and the output voltage cannot be stabilized. When the DPWM resolution is high, the quantized value of the output voltage ${V}_{\mathrm{H}}$ can reach ${E0}$. At this time, the control loop realizes zero error, and the output voltage is stable.
On the other hand, what affects the output accuracy and stability of DPWM is its linearity. As shown in Fig. 3, when the resolution of DPWM has high non-linearity, its resolution deviation exceeds the resolution of ADC, the quantized value of the output voltage ${V}_{\mathrm{N}}$ cannot reach ${E0}$, which will also cause the decrease in output voltage accuracy and limit cycle oscillation.
Therefore, it is essential to realize high-resolution and high-linearity DPWM to improve the performance of high-frequency switching converters.
Digital controllers for switching converters are usually implemented with specific control chips. Current solutions for implementing high-precision DPWM are based on application-specific integrated circuits (ASICs) or provided as peripherals in microcontrollers, such as Texas Instrument TMS320F28035. However, ASICs have additional design costs, and microcontrollers have limited functionality. In addition, future iterations of technology updates require more significant costs. On the other hand, by constructing a high-resolution DPWM module and instantiating it in a field programmable gate array (FPGA), high-resolution DPWM output can be realized. FPGA has the feature of configurable programming. When it is necessary to improve the existing design or add new functions, it only needs to redesign the code and load it into the FPGA to realize the required functions without updating and iterating the hardware. FPGA has the characteristics of high flexibility and strong scalability, which makes it more and more widely used in switching converters.
The traditional way of generating DPWM signals based on FPGA is the counter comparison method, as shown in Fig. 4. It has the advantages of simple structure, less resource utilization, and high linearity. However, its minimum pulse time resolution is limited by the maximum clock frequency of the FPGA, given by (1), ${T}_{\text{step }}$ is minimum pulse time resolution, and ${f}_{\text{clk }}$ is the clock frequency for the counter.
${T}_{\text{step }}= \frac{1}{{f}_{\text{clk }}}$
With the development of FPGA technology, the clock frequency that FPGA can support is getting higher and higher, reaching $\mathrm{{GHz}}$. Even if the clock frequency reaches $\mathrm{{GHz}}$, its minimum pulse time resolution only reaches the ns level, which does not significantly improve the resolution. Moreover, as the clock frequency increases, the cost of FPGA increases dramatically, which is unfavorable for the application of switching converters.
In recent years, many papers have proposed different methods based on FPGA to obtain smaller pulse time resolution. Table I summarizes the characteristics of these methods. These methods can be mainly divided into three types.
1) Based on phase-shifted clock: The first type utilizes the phase-locked loop (PLL) or digital clock management (DCM) unit of FPGA to generate phase-shifted clocks to construct delay lines for high-resolution DPWM signals, As shown in Fig. 5. The resolution of DPWM based on phase-shifted clock depends on the clock frequency and the number of clocks.[4] achieves ${12.5}\mathrm{\;{ns}}$ resolution with PLL. It uses eight ${10}\mathrm{{MHz}}$ phase-shifted clocks to construct eight phase-shifted carrier counters, which consumes many resources. The critical path contains two multiplexers, and there is no compensation for the delay deviation of the critical path. The delay deviation of DPWM is significant, and the linearity is low. Moreover, the clock signal’s double-edge triggering capability has yet to fully develop.[5] and [6] use four 128MHz phase-shifted clocks to achieve higher resolution, which reaches $2\mathrm{{ns}}$. The critical path was not compensated, and its linearity was 0.994 with a resolution deviation of 450ps in [6]. To improve the linearity of DPWM,[5] uses manual placement and routing to compensate for the delay deviation of the critical path, and the resolution deviation is reduced to 350ps. In order to achieve a higher resolution,[3] uses three cascaded DCMs, and its resolution reaches 156 ps at a clock of 100 MHz. However, multi-stage multiplexers are on the critical path of the cascaded structure, which significantly reduces the DPWM linearity. Moreover, there is no compensation for the critical path.[7] proposes a DPWM structure with a time step of 19.5ps based on the DCM of Xilinx FPGAs. The main disadvantage of the DPWM architecture is that the phase shift time of the clock must be dynamically updated when the duty cycle changes. Increasing update speed requires multiple phase-shifted clocks, and the presence of multiplexers in the critical path will reduce linearity.
2) Based on delay line: As shown in Fig. 6, the second approach uses the logic element or IDELAYE to obtain a delay line. This method can also generate high-resolution DPWM signals, and it does not use the internal PLL or DCM in FPGA and is not limited by the clock frequency.[14] uses two IDELAYE2 blocks to achieve a resolution of 19.5 ps.[20] implements complementary DPWM signals using four IDELAYE blocks, the time resolution for the Artix-7 is 79.6 ps, and the Kintex-UltraS-cale 7 is 4.72 ps. IDELAYE block is an IP officially provided by Xilinx that can be used to delay specific signals, so the method of using the IDELAYE block to realize high-precision DPWM can only be applied to FPGAs of the Xilinx series.[8] and [9] use the adder carry method to achieve fine delay adjustment with a resolution of less than 100ps. However, this method requires additional layout and routing constraints for the fine delay unit, which is complex to implement and needs better versatility.[10],[15],[19],[22] and [23] adopt similar structures, and cascaded logic gates realize their fine delay elements. The inconsistency of the delay line and the presence of multiplexers on critical paths will lead to poor linearity.
3) Based on phase-shifted clock and delay line: In addition to these two main methods, high-resolution DPWM is also achieved by using the hybrid structure method, which has some of the advantages of the above two methods and improves the overall performance, as shown in Fig. 7.
In order to improve the critical path delay deviation,[16] uses hardware combinational logic to achieve duty cycle accuracy compensation, and [11] implements critical path optimization through manual layout and routing.[17] proposes a synchronous phase-shifted circuit to optimize the critical path of the phase-shifted clock. Moreover, its implementation is complex.
Previous studies found that the phase-shifted clock-based method has good versatility. However, there is a common problem: the presence of multiplexers on the critical path, resulting in large delay deviations and reducing the linearity of DPWM. The method based on the delay line structure usually requires a complex manual layout and routing constraints on the delay path of the delay line or uses a specific type of FPGA to achieve fine delay. The device speed grade significantly affects the resolution, and the versatility is low. Although the hybrid architecture can improve the accuracy of DPWM, it also needs to optimize the delay of the critical path, and the implementation is complicated.
When the switching frequency of DPWM is up to MHz or higher, the time resolution will reach the picosecond level. Moreover, the delay time deviation of the critical path caused by the logic unit and interconnection will be greater than the time resolution of DPWM, which will cause serious non-linearity of DPWM. The inconsistency of DPWM output pulse width changes will lead to limit cycle oscillation and affect the regulation performance of the converter.
Considering the application of a high-frequency power electronic converter, the modulation of DPWM needs to have good universality, low complexity, high output accuracy, and high linearity. To actualize the above performances, the paper presents a simplified structure with an improved critical path optimization, which has the advantages of high linearity, easy implementation, less logical resource occupation, and simplicity of transplantation. The main contribution of the method proposed in this paper is to construct a simplified clock synchronization multiplexer and phase-shifted DPWM signal synchronization selector, which improves the delay deviation of the traditional multiplexer in the critical path.
The structure of this paper is as follows: Section II describes the architecture and application of the proposed implementation method. Section III illustrates the implementation of linearity optimization and provides a comparative analysis with traditional multiplexer method. Section IV evaluates and verifies the performance of the proposed method through simulation and experiment. Finally, Section V concludes the paper.
II. Proposed DPWM Architecture and Application
Less
Fig. 8 shows the control architecture of the proposed DPWM signal modulation method. It consists of a decoder, a phase-shifted clock whose phase is delayed ${180}^{\circ }$ $D\left\lbrack {m - 1 : 0}\right\rbrack /{2}^{m}$ by the internal PLL of the FPGA, a reference PWM signal generating unit, and a phase-shifted PWM unit. $D\left\lbrack {n - 1 : 0}\right\rbrack$ is the input duty cycle signal. $D\left\lbrack {n - 1 : m + 1}\right\rbrack$ is used to generate a reference PWM signal, which is denoted as ${\mathrm{{PWM}}}_{\text{Ref }}$. $D\left\lbrack m\right\rbrack$ is a flag-selected data bit that enables the corresponding phase-shifted PWM signal. $D\left\lbrack {m - 1 : 0}\right\rbrack$ is used to select the phase-shifted clock, denoted as ${\mathrm{{CLK}}}_{\theta }$. ${\mathrm{{CLK}}}_{\text{in }}$ is the input clock signal of FPGA for PLL. PWM ${}_{\text{Output }}$ is the output signal.
As Fig. 8 shows, the PLL generates clocks of the same frequency and different phases. The ${\mathrm{{PWM}}}_{\text{Ref }}$ is generated with the clock of a ${0}^{\circ }$ phase-shifting angle. The corresponding phase-shifted clock ${\mathrm{{CLK}}}_{\theta }$ is selected according to the signal $D\left\lbrack {m - 1 : 0}\right\rbrack$, and the phase-shifted clock ${\mathrm{{CLK}}}_{\theta }$ shifts the phase of ${\mathrm{{PWM}}}_{\text{Ref }}$ by $\theta$. The high-resolution PWM signal ${\mathrm{{PWM}}}_{\text{Output }}$ is constructed in the phase-shifted PWM unit.
In this section, the implementation of the proposed method will be introduced in detail.
A. Decoder Operation
The function of the decoder M1 is to turn input $D\left\lbrack {n - 1 : 0}\right\rbrack$ into three parts, which are the most significant bits $D\left\lbrack {n - 1 : m + 1}\right\rbrack$, the intermediate significant bit $D\left\lbrack m\right\rbrack$, the least significant bits $D\left\lbrack {m - 1 : 0}\right\rbrack .D\left\lbrack {n - 1 : m + 1}\right\rbrack$ is the modulated signal used to generate ${\mathrm{{PWM}}}_{\text{Ref }}$ under the rising edge of ${\mathrm{{CLK}}}_{0}D\left\lbrack m\right\rbrack$ is the control signal used to select the reference ${\mathrm{{PWM}}}_{\text{Ref }}$ as ${\mathrm{{PWM}}}_{p}$ or ${\mathrm{{PWM}}}_{n}$ and then shift the phase of ${\mathrm{{PWM}}}_{\text{Ref }}$ through ${\mathrm{{CLK}}}_{\theta }$, as Table II shows. $D\left\lbrack {m - 1 : 0}\right\rbrack$ is divided into two parts by decoder M2: the Clkselect and Ena. The Clkselect is used to select the clock from PLL, and the Ena enables the corresponding outclk clock signal, according to Table III.
B. Phase-Shifted Clock Configuration and Selection
In the phase-shifted clock unit, the clock signal with the high-resolution phase-shifting angle is generated, which is used to perform phase-shifting processing of the ${\mathrm{{PWM}}}_{\text{Ref.}}$
1) PLL Configuration: There are configurable hardware PLL modules in FPGA chips. Different FPGAs can support different numbers of PLL. Generally, the number of supported PLL is 2 or 4 in FPGA, and each PLL can generate 5 clocks with different frequencies and phases. It can be configured according to actual needs.
The number of PLL selected is ${N}_{\mathrm{P}}$ and the number of clocks that each PLL can generate is ${N}_{\mathrm{C}}$ in this paper. To reduce the computational complexity and optimize the resource utilization of FPGA, the number of phase-shifting clocks ${N}_{\mathrm{P}}$ and ${N}_{\mathrm{C}}$ is selected as a multiple of 2, and the total number of clocks that can be generated is ${2}^{m}$ :
${2}^{m}= {N}_{\mathrm{C}}\times {N}_{\mathrm{P}}$
The phase offset of adjacent phase-shift clocks is ${\theta }_{\mathrm{C}}$ :
${\theta }_{\mathrm{C}}= {180}^{\circ }/{2}^{m}$
The phase delay of adjacent phase-shift clocks is ${T}_{\mathrm{P}}$ :
${T}_{\mathrm{P}}= {T}_{\mathrm{C}}/{2}^{m + 1}$
The ${T}_{\mathrm{C}}$ is the period of the clock from PLL.
2) Clock Selection: To improve the nonlinear effect caused by excessive delay deviation of conventional MUX, this paper proposes a logically symmetric MUX whose basic unit contains dedicated clock control blocks and logical OR gates.
The dedicated clock control block is a unique clock selector with excellent symmetry. It can dynamically select the input clock signal and has the function of enabling the output signal. Most FPGAs are configured with this feature. The dedicated clock control blocks for Altera and Xilinx series FPGAs are shown in Fig. 9.
The altclkctrl (ALT) is a clock control block in Altera FPGA with a clock control function. With the Quartus II MegaWizard Plug-In Manager, the clock control block can be easily configured in supported devices. It is available for Arria 10, Arria II GX, Arria II GZ, Arria V, Arria V GZ, Cyclone III, Cyclone III LS, Cyclone IV E, Cyclone IV GX, Cyclone V, Cyclone 10 LP, Stratix IV, Stratix V, and MAX 10 device series.
Similar clock control blocks in FPGAs of other manufacturers, such as BUFGCTRL in Xilinx FPGA, can achieve the same function as the ALT block in Altera FPGA.
This paper uses ALT in Altera FPGA as an example to introduce the proposed synchronous clock phase shifting method. When ALT uses multiple input sources, the $\operatorname{In}\left\lbrack x\right\rbrack$ ports can only be driven by the dedicated clock input pins and the PLL clock outputs. Dedicated clock input pins must feed only $\operatorname{In}\left\lbrack 0\right\rbrack$ and $\operatorname{In}\left\lbrack 1\right\rbrack$, while the PLL clock outputs must feed only $\operatorname{In}\left\lbrack 2\right\rbrack$ and $\operatorname{In}\left\lbrack 3\right\rbrack$. In this article, $\operatorname{In}\left\lbrack 2\right\rbrack$ and $\operatorname{In}\left\lbrack 3\right\rbrack$ are used to form a two-toone multiplexer for selecting phase-shifted clocks from PLL.
As is shown in Fig. 10 and Table III, the phase-shifted clock from the PLL is selected by Clkselect, and the valid Outclk signal is output by the enable signal Ena in ALT. Turn off the Outclk clock by Ena in the unused ALT block. That is, only one ALT is working at the same time, and only one effective clock signal is output to ensure that the output clock signals of multiple ALT modules do not affect each other, and then pass through a symmetrical logic OR gate to obtain the phase-shifted clock signal ${\mathrm{{CLK}}}_{\theta }$.
C. The Reference PWM Signal Generation
The function of the reference PWM signal generation unit is to construct a coarse adjustment signal ${\mathrm{{PWM}}}_{\text{Ref }}$ for a high-resolution PWM signal, as shown in Fig. 11. The timing diagram is shown in Fig. 12.
1) Carrier Counter: Select the clock signal ${\mathrm{{CLK}}}_{0}$ as the reference clock, and use the rising edge of the ${\mathrm{{CLK}}}_{0}$ to generate a carrier counter. The period of the carrier counter is denoted as ${T}_{\mathrm{S}}$. The carrier counter starts counting from 0, increasing by 1 for each reference clock cycle until the count period reaches ${T}_{\mathrm{s}}$ and the carrier counter is set to 0 . Then, repeat the next cycle of counting.
2) Comparator: The value of the modulated signal is expressed as $D\left\lbrack {n - 1 : m + 1}\right\rbrack$. When the Cnt value of the carrier counter is greater than $D\left\lbrack {n - 1 : m + 1}\right\rbrack$, the PWM output is at a low level. Otherwise, the PWM output is at a high level, and the reference PWM signal generated by this method is recorded as ${\mathrm{{PWM}}}_{\text{Ref }}$ :
${\mathrm{{PWM}}}_{\text{Ref }}= \left\{\begin{array}{ll} 0 & D\left\lbrack {n - 1 : m + 1}\right\rbrack \leq \mathrm{{Cnt}}\\ 1 & D\left\lbrack {n - 1 : m + 1}\right\rbrack >\mathrm{{Cnt}}\end{array}\right.$
D. The Phase-Shifted PWM Signal Construction
As described in Fig. 13, the accurate delay time of the reference ${\mathrm{{PWM}}}_{\text{Ref }}$ signal is achieved by using the phase-shifted clock ${\mathrm{{CLK}}}_{\theta }$.
At the rising edge of the phase-shifted clock ${\mathrm{{CLK}}}_{\theta }$, the reference ${\mathrm{{PWM}}}_{\text{Ref }}$ signal is phase-shifted by $\theta$ with FF1, expressed as ${\mathrm{{PWM}}}_{p}$.
Similarly, at the falling edge of the phase-shifted clock ${\mathrm{{CLK}}}_{\theta }$, the reference ${\mathrm{{PWM}}}_{\text{Ref }}$ signal is phase-shifted by $\theta +{180}^{\circ }$ with FF2, which is expressed as ${\mathrm{{PWM}}}_{n}$.
In this paper, a synchronous two-to-one multiplexer is proposed, as shown in Fig. 13, to select the PWM signal while avoiding the influence of delay deviation caused by using a multiplexer. The selection signal $D\left\lbrack m\right\rbrack$ is placed at the front end of flip-flops FF1 and FF2. The ${\mathrm{{PWM}}}_{\text{Ref }}$ is sent to the data port D of the flip-flop after being selected by the AND gate G4 and the AND gate G5. Under the flip-flop’s clock synchronization, the AND gate’s logic delay effect is eliminated.
When $D\left\lbrack m\right\rbrack$ is 0, the output signal of AND gate G4 is PW- ${\mathrm{M}}_{\text{Ref }}$, and the output signal of AND gate G5 is 0 . On the rising edge of ${\mathrm{{CLK}}}_{\theta }$, the ${\mathrm{{PWM}}}_{\text{Ref }}$ signal is output as ${\mathrm{{PWM}}}_{p}$ through the flip-flop FF1, and the output port data of the flip-flop FF2 is 0. That is, ${\mathrm{{PWM}}}_{n}$ is 0 .
When $D\left\lbrack m\right\rbrack$ is 1, the output signal of AND gate G4 is 0, and the output signal of AND gate G5 is ${\mathrm{{PWM}}}_{\text{Ref }}$. On the falling edge of ${\mathrm{{CLK}}}_{\theta }$, the ${\mathrm{{PWM}}}_{\text{Ref }}$ signal is output as ${\mathrm{{PWM}}}_{n}$ through flip-flop FF2, and the output port data of flip-flop FF1 is 0 . That is, ${\mathrm{{PWM}}}_{p}$ is 0 .
After the output signals of flip-flops FF1 and FF2 pass through the symmetrical logic OR gate G6, the desired phase-shifting ${\mathrm{{PWM}}}_{pn}$ signal can be selected.
After the phase-shifted ${\mathrm{{PWM}}}_{pn}$ signal and the ${\mathrm{{PWM}}}_{\text{Ref }}$ signal are processed by the OR gate G7, the high-resolution ${\mathrm{{PWM}}}_{\text{Output }}$ signal can be obtained as follows:
${\mathrm{{PWM}}}_{\text{Output }}= \left\{\begin{array}{ll}{\mathrm{{PWM}}}_{\text{Ref }}\mid {\mathrm{{PWM}}}_{p}& D\left\lbrack m\right\rbrack = 0 \\{\mathrm{{PWM}}}_{\text{Ref }}\mid {\mathrm{{PWM}}}_{n}& \mathrm{D}\left\lbrack m\right\rbrack = 1 \end{array}\right.$
The timing diagram of the fine adjustment ${\mathrm{{PWM}}}_{\text{Output }}$ signal is shown in Fig. 14.
E. Pulse Width of the Proposed Method
According to the proposed method, when using PLL to generate ${2}^{m}$ phase-shifted clocks, the phase deviation of adjacent phase-shifted clocks is ${180}^{\circ }/{2}^{m}$. Select the required phase-shifted clock ${\mathrm{{CLK}}}_{\theta }$ by the proposed symmetrical clock multiplexer.
The pulse width resolution of the ${\mathrm{{PWM}}}_{\text{Output }}$ is ${T}_{\mathrm{P}}$, as shown in (4). The pulse width ${T}_{\mathrm{{PW}}}$ of ${\mathrm{{PWM}}}_{\text{Output }}$ is expressed as:
${T}_{\mathrm{{PW}}}= D\left\lbrack {n - 1 : m + 1}\right\rbrack \times {T}_{\mathrm{C}}+ D\left\lbrack {m : 0}\right\rbrack \times {T}_{\mathrm{P}}$
The method proposed in this paper improves the pulse width resolution by a factor of ${2}^{m + 1}$.
F. Timing Diagram of the Proposed Method
By configuring the PLL, the clock signal with phase-interleaved delay is generated. Taking ${N}_{\mathrm{P}}= 2$ and ${N}_{\mathrm{C}}= 4$ as an example, then $m = 3$, the input modulation signal $\mathrm{D}\left\lbrack {n - 1 : 0}\right\rbrack$ takes 85 in decimal and 1010101 in binary, then the value of $n$ is 7 . This way, eight channels of phase-shifted clock signals with the same frequency and interleaved delay phase with ${22.5}^{\circ }$ are generated. $D\left\lbrack {n - 1 : m + 1}\right\rbrack$ is 101 in binary, and the pulse width of ${\mathrm{{PWM}}}_{\text{Ref }}$ signal is $5{T}_{\mathrm{C}}$. According to Table II, $D\left\lbrack {m - 1 : 0}\right\rbrack$ is 101 in binary, and the ${\mathrm{{CLK}}}_{\theta }$ is selected as ${\mathrm{{CLK}}}_{{180}^{\circ }}\cdot \left({{2}^{m}- 3}\right)/{2}^{m}$. When $m = 3$, the ${\mathrm{{CLK}}}_{\theta }$ is ${\mathrm{{CLK}}}_{{112.5}^{\circ }}D\left\lbrack m\right\rbrack = 0$, the ${\mathrm{{PWM}}}_{\text{Ref }}$ signal is phase-shifted by ${112.5}^{\circ }$ on the rising edge of ${\mathrm{{CLK}}}_{{112.5}^{\circ }}$ to obtain ${\mathrm{{PWM}}}_{p}$. The high-resolution ${\mathrm{{PWM}}}_{\text{Output }}$ signal can be obtained as (6) is ${\mathrm{{PWM}}}_{\text{Ref }}{\mathrm{{PWM}}}_{p}$. The pulse width of the ${\mathrm{{PWM}}}_{\text{Output }}$ as (7) is $5{T}_{\mathrm{C}}+ 5{T}_{\mathrm{P}}$.
The waveform of each stage of generating high-resolution ${\mathrm{{PWM}}}_{\text{Output }}$ is shown in Fig. 15.
III. Linearity and Power Consumption Optimization With Proposed Method
Less
A. Critical Path Analysis
In the high-resolution PWM signal generation method, the phase-shifting circuit is the critical path that affects the linearity of the PWM signal. In the traditional multiplexer method, the combinational logic in the critical path deteriorates the linearity of the PWM signal, as shown in Fig. 16.
1) The asymmetric critical path caused by the selection unit of the phase-shift clock ${\mathrm{{CLK}}}_{\theta }$ : In the previous work, the multiplexer is usually composed of combinational logic to select the phase-shift clock, and LUT implements this combinational logic in FPGA. Depending on the FPGA, either 4-input or 6-input LUTs can be used. The 4-input LUT can form a 2-to-1 multiplexer, and the 6-input LUT can form a 4-to-1 multiplexer. In this article, using Altera Cyclone-IV series FPGA with 4-input LUT, the LUT unit’s delay deviation range from different input ports to output ports is0.15ns to ${0.5}\mathrm{\;{ns}}$. LUTs are combined in cascaded structures when multiplexers for more inputs are required. Synthesis tools will synthesize the multiplexer into an asymmetric structure, and the critical path delay of the phase-shifted clock selection unit will have a more significant deviation.
2) The asymmetric critical path caused by the selection unit of the phase-shifted ${\mathrm{{PWM}}}_{pn}$ signal: To generate the higher-resolution PWM signal, this paper uses the double-edge trigger function of the phase-shifted clock ${\mathrm{{CLK}}}_{\theta }$ to generate two phase-shifted ${\mathrm{{PWM}}}_{pn}$ signals. Then, select the required phase-shift PWM signal through the multiplexer. The traditional multiplexer uses a 4-input LUT unit to form a 2-to-1 multiplexer, and the critical path has a delay deviation of ${0.15}- {0.5}\mathrm{{ns}}$.
B. Critical Path Optimization
Due to the asymmetric structure of the traditional multiplexer, it will bring a more significant delay deviation, which is unsuitable for high-resolution PWM signals.
According to the method proposed in this paper, the linearity of the PWM signal can be significantly improved by optimizing the design of the selection unit with the symmetrical multiplexer. The logic symmetrical multiplexer for clock selection and synchronous 2-to-1 selector for phase-shifted PWM in verilog code is shown in Appendix A.
1) Logic Symmetrical Multiplexer: The proposed method uses eight clocks from the PLL, and an 8-to-1 multiplexer needs to be constructed. For better illustration, the logic symmetric multiplexer in Fig. 10 is redrawn, as shown in Fig. 17.
The 8-to-1 multiplexer is divided into two parts. The first part uses the ALT IP core to select the clock signal from the PLL dynamically. As a unique clock selector, the ALT module can avoid the jitter of dynamic selection. Moreover, the logic delays from different clock input ports to output ports are entirely consistent. The ALT module has four input ports, only the $\operatorname{In}\left\lbrack 2\right\rbrack$ and $\operatorname{In}\left\lbrack 3\right\rbrack$ ports are allowed to access the PLL clock signal. To select eight clocks, use four ALT modules to construct four 2-to-1 clock selectors. Enable the corresponding ALT module according to Ena port. That is, only one input signal is output from four ALT modules simultaneously. The second part is composed of two-level logic OR gates. The function of the logic OR gate is to combine the output signals from the four ALT modules to ensure that the input signal can come from any ALT module. These logic OR gates are implemented by LUT units. Through timing analysis, although the delay deviations of the four input ports of the LUT in FPGA are different, the path delay deviation of the DATAA and DATAB ports are small. The 2-input OR gate can be formed by using the DATAA and DATAB ports with LUT, as shown in Fig. 18. By using 3 LUT units combined into a 4-input OR gate with a symmetrical structure, the delay deviation can be reduced.
The traditional multiplexer structure uses 7 LUT units, and the critical delay path with combinational logic contains three levels of LUTs. The logically symmetric multiplexer proposed in this paper only uses three LUT units, and the critical delay path of combinational logic is reduced to a two-stage LUT. The non-linear influence caused by the delay deviation of the clock multiplexer is significantly reduced.
2) Synchronous 2-to-1 selector: The Synchronous 2-to-1 selector in Fig. 13 is redrawn as shown in Fig. 19. The selection signal is placed at the front end of the flip-flop, and under the clock signal synchronization, the delay effect caused by the selection signal is eliminated. The function of the two-input OR gate G6 combines the outputs of the two flip-flops. The critical path of the synchronous 2-to-1 selector has only one logic OR gate, and the delay deviation of the combinational logic will be significantly improved.
3) Placement and route constraints and the assignment of LUT input port: By optimizing the design of the selection unit in the critical path, the critical path of the synthesized clock selector and phase-shift PWM signal selector is logically symmetrical. In addition to considering the symmetry of the circuit structure, it is also necessary to ensure that the wiring delay of the combinational logic in the critical path is symmetrical. After optimization with the proposed method, the critical path of the clock selector contains three logical OR gates, and the critical path of the phase-shift PWM signal selector has one logical OR gate. Compared with traditional multiplexer method, the method proposed in this paper uses fewer logic gates and simpler placement and routing constraints.
According to the above analysis, the delay deviation of the DATAA and DATAB ports of the 4-input LUT unit is slight. However, the input port of the logical OR gate synthesized by the synthesis tool is not necessarily the DATAA and DATAB ports. Therefore, it is also necessary to allocate the ports of the 4-input LUT unit and ensure the input ports of the logic OR gate are DATAA and DATAB to minimize the delay deviation of the critical path.
3.1 Placement and route constraints
The delay deviation of the critical path is reduced by placements and routing constraints on the four logic OR gates.
The logic OR gates G1, G2, and G3 are symmetrically placed in the same Logiclock regions, and each BLOCK of the FPGA allows simultaneous access to two global clock signals. Therefore, the Logicclock regions are set to 3 BLOCKs to ensure the minimum delay of the clock signals connected to the logic OR gates G1, G2, and G3. Similarly, the flip-flops FF1 and FF2 and the logic OR gate G6 are symmetrically placed in the same Logicclock regions.
Using the Logiclock assignment function to fix the logic OR gates at the designated location of the FPGA to ensure that the path delays of the logic OR gates after compilation remain unchanged. The logic OR gates are placed symmetrically to reduce delay deviation. The location constraints of the logiclock are shown in Fig. 20(a).
3.2 The assignment of LUT input port
As shown in Fig. 20(b), use the Resource Property Editor to redistribute LUT input port signals and edit the logical relationship between input and output signals. In Connectivity, set LUT’s DATAA and DATAB ports as input ports, and in Combinational, set the LUT’s input and output signal relationship to OR logic. The configuration of logic OR gates G1, G2, G3, and G6 is completed as described above.
C. Critical Path Delay Comparison
The path delay comparison between the optimized selector proposed in this paper and the traditional multiplexer is shown in Fig. 21. For the selection unit of the phase-shifted clock ${\mathrm{{CLK}}}_{\theta }$, the maximum delay deviation by the traditional multiplexer is ${1.135}\mathrm{\;{ns}}$, and the method proposed in this paper is ${60}\mathrm{{ps}}$. For the selection unit of the phase-shifted ${\mathrm{{PWM}}}_{pn}$ signal, the maximum delay deviation by the traditional multiplexer is ${0.164}\mathrm{\;{ns}}$, and the method proposed in this paper is $9\mathrm{{ps}}$. The proposed method has better symmetry and minor delay deviation in the critical path.
D. Power Consumption Optimization
The proposed method uses eight clocks of the PLL. Using traditional multiplexers, the power consumption of FPGA is relatively large and requires eight clocks to work simultaneously. The optimized method prohibits the unused clock output by using the enable function of the ALT module to ensure that only one phase-shifted clock works simultaneously. The power consumption of FPGA can be reduced. Power consumption was evaluated using the PowerPlay Early Power Estimator, as shown in Fig. 22 and Table IV.
IV. Performance Evaluation and Experimental Results of the Proposed Method
Less
According to the proposed method, the program design is completed in the different FPGA. By timing analysis and critical path optimization, the high-resolution DPWM is realized. It is verified by simulation and experiments.
A. Simulation Results
The detailed simulation parameters are as follows:
• The reference clock frequency: ${200}\mathrm{{MHz}}$
• The modulation signal $\mathrm{D}\left\lbrack {n - 1 : 0}\right\rbrack :{85}$
• PWM signal switching frequency: 1 MHz.
The simulation waveform of Cyclone IV FPGA is shown in Fig. 23(a), and the simulation waveform of Atrix7 FPGA is shown in Fig. 23(b). The period of the reference clock is $5\mathrm{\;{ns}}$, and the single-step adjustment resolution of ${\mathrm{{PWM}}}_{\text{Output }}$ is 312.5 ps. The value of $D\left\lbrack {n - 1 : 0}\right\rbrack$ takes 85 in decimal,1010101 in binary. $D\left\lbrack {n - 1 : m + 1}\right\rbrack$ is 101 in binary, $D\left\lbrack m\right\rbrack$ is 0, and $D\left\lbrack {m - 1}\right\rbrack$ is 101. The ${\mathrm{{CLK}}}_{\theta }$ comes from ${\mathrm{{CLK}}}_{{112.5}^{\circ }}$. The ${\mathrm{{PWM}}}_{\text{Ref }}$ is shifted to 1.562 ns with ${\mathrm{{CLK}}}_{{112.5}^{\circ }}$. The pulse width of ${\mathrm{{PWM}}}_{\text{Output }}$ is ${26.562}\mathrm{\;{ns}}$.
B. Experimental Results
1) Experiments Results for the Cyclone IV FPGA
To verify the performance of the proposed method, experiments were carried out on the Cyclone IV FPGA.
The pulse width test results of the traditional multiplexer method and the proposed method in the Cyclone IV FPGA are shown in Fig. 24, and the modulation signal $D\left\lbrack {n - 1 : 0}\right\rbrack$ of DPWM changes from 16 to 127. The linearity of the traditional multiplexer is 0.99951, and the linearity of the proposed method is 0.99999, which is close to 1 .
The high-resolution DPWM signal is constructed by the phase-shifted ${\mathrm{{PWM}}}_{pn}$ signal generated by the ${\mathrm{{CLK}}}_{\theta }$ and the ${\mathrm{{PWM}}}_{\text{Ref }}$ signal generated by ${\mathrm{{CLK}}}_{0}$. As shown in Fig. 25, the delay path of the ${\mathrm{{CLK}}}_{0}$ and ${\mathrm{{CLK}}}_{\theta }$ are inconsistent, which will cause a constant pulse width deviation ${T}_{\mathrm{{CO}}}$ between the high-resolution DPWM signal and the ideal DPWM signal.
As shown in Fig. 26(a), there is a constant delay deviation between the high-resolution DPWM signal proposed in this paper and the ideal DPWM signal. According to the architecture proposed in this paper, by setting an initial offset for the modulation signal $D\left\lbrack {n - 1 : 0}\right\rbrack$, the constant pulse width deviation ${T}_{\mathrm{{CO}}}$ can be easily compensated. The constant pulse width deviation does not affect the linearity and resolution of the high-resolution PWM signal. Therefore, no compensation is made for the constant pulse width deviation in this paper.
The pulse signal varies from 11.286 ns to 21.052 ns of DPWM by the traditional multiplexer, as shown in Fig. 26(b), the modulation signal $D\left\lbrack {n - 1 : 0}\right\rbrack$ changes from 0000_0010_0000 to 0000_0011_1111 in binary, which is from 32 to 63 in decimal, and the non-linear deviation of the pulse width is relatively large.
The pulse signal waveform of DPWM by the method proposed in this paper is shown in Fig. 26(c) with the same changing modulation signal $D\left\lbrack {n - 1 : 0}\right\rbrack$. The pulse width varies uniformly from 11.547 ns to 21.240 ns with the modulation signal $D\left\lbrack {n - 1 : 0}\right\rbrack$ and has excellent linearity. Taking $D\left\lbrack {n - 1 : 0}\right\rbrack =$ 63 in decimal as an example, the $D\left\lbrack {n - 1 : m + 1}\right\rbrack = 3$, the $D\left\lbrack m\right\rbrack =$ 1, the $D\left\lbrack {m : 0}\right\rbrack ={15}$, and the pulse width ${T}_{\mathrm{{PW}}}$ is: ${T}_{\mathrm{{CO}}}+ 3 \cdot {T}_{\mathrm{C}}+$ ${15}\cdot {T}_{\mathrm{P}}= {1.538}\mathrm{{ns}}+ {3.5}\mathrm{{ns}}+ {15.0.3125}\mathrm{{ns}}= {21.2255}\mathrm{{ns}}$, the absolute error of the pulse width is ${21.24}\mathrm{\;{ns}}- {21.2255}\mathrm{\;{ns}}= {0.0145}\mathrm{\;{ns}}$.
When the absolute error of the pulse width is considered, the effect of constant delay deviation ${T}_{\mathrm{{CO}}}$ between the ${\mathrm{{PWM}}}_{\text{Ref }}$ signal and the phase-shifted ${\mathrm{{PWM}}}_{pn}$ signal can be ignored. Fig. 27 shows the pulse width absolute error of DPWM without ${T}_{\mathrm{{CO}}}$ with the modulation signal $D\left\lbrack {n - 1 : 0}\right\rbrack$ from 16 to 127. The maximum absolute pulse width deviation between the high-resolution DPWM signal generated by the traditional multiplexer and the ideal DPWM signal is 0.4765ns. The maximum absolute pulse width deviation is 48.5ps with the proposed method. According to the architecture proposed in this paper, the DPWM signal will be fine-tuned at a $1/{16}$ clock cycle. The experimental results show that the proposed method achieves high-resolution PWM output with high linearity in the Cyclone IV FPGA.
2) Experiments Results for the Atrix7 FPGA
In order to better illustrate the versatility of the proposed method. The same experimental verification was performed on Atrix7 series FPGA from Xilinx, the cascaded BUFGCTRL is used to replace the ALT realize the selection of the phase-shifted clock from the PLL. The experimental results are shown in Fig. 28. The pulse width varies with the modulation signal D[n-1:0] changes from 0000_0010_0000 to 0000_0011_1111 in binary, which is from 32 to 63 in decimal are shown in Fig. 28(a). As shown in Fig. 28(b), the linearity reaches 0.99999, which is close to 1. Fig. 28(c) shows the pulse width absolute error of DPWM without ${T}_{\mathrm{{CO}}}$, and the maximum absolute pulse width deviation is 20.5ps with the proposed method in the Atrix7 FPGA.
The experimental results show that the proposed method can achieve high-resolution PWM output and high linearity in different FPGAs, and has good versatility.
C. Resource Occupancy of FPGA
According to the above method, the high-resolution DPWM can be simply realized. The maximum value of modulation signal $D\left\lbrack {n - 1 : 0}\right\rbrack$ is 3200 in decimal with a switching frequency of $1\mathrm{{MHz}}$. The effective bits of the DPWM are close to 12 bits. The high-resolution DPWM module uses 63 LUTs (0.61%), 27 FFs (0.26%), 2 PLL modules, and 4 ALT modules, taking up fewer resources with the available 10320 logic element in the Cyclone IV FPGA. The high-resolution DPWM module uses 39 LUTs, 27 Registers, 2 PLL modules, and 7 BUFGCTRL modules in the Atrix7 FPGA.
D. Comparative Analysis With Different DPWM Method
Table V summarizes the performance comparison based on the phase-shifted clock and the proposed methods. The degree of difficulty from easy to difficult: extremly easy, easier, generally easy, difficult.
[4] achieves ${12.5}\mathrm{\;{ns}}$ resolution with ${10}\mathrm{{MHz}}$ clock frequency. If the clock frequency in [4] is increased to ${200}\mathrm{{MHz}}$, the resolution becomes ${625}\mathrm{{ps}}$. Compared with [4], this paper makes full use of the double-edge triggering of the phase-shifted clock to achieve a lower resolution, and the resolution is reduced to 312.5 ps.
[5] and [6] use a 128 MHz clock to achieve a resolution of $2\mathrm{\;{ns}}$, and there is a multiplexer on the critical path. The linearity of [6] is low, and the linearity deviation is large, reaching ${450}\mathrm{{ps}}$. Although [5] uses manual placement and routing to compensate for the critical path delay deviation, the resolution deviation is still large, reaching ${350}\mathrm{{ps}}$.
[13] uses two methods to construct high-resolution DPWM. The first method is to use DCM to construct four reference phase-shift clocks and use eight D-triggers to generate 8-way phase-shift delay circuits with a resolution of ${625}\mathrm{{ps}}$, and its linearity is limited by the D-triggers and multiplexers on the critical path. The second method uses LUT units to construct a delay circuit with a resolution of ${500}\mathrm{{ps}}$, and its resolution is limited by the device’s speed level. These two methods are simple in structure but require strict layout and routing constraints on D-triggers, multiplexers, and LUT units.
[3] uses multiple cascaded DCMs to achieve a resolution of ${156}\mathrm{{ps}}$. There are multi-stage multiplexers on the critical path, which greatly reduces linearity. The more DCMs used, the greater the linearity deviation.
In order to obtain a higher DPWM resolution,[16],[17] use a hybrid DPWM architecture, which consists of a first-stage phase-shift clock and a second-stage adder carry chain.[11] carried out manual layout and routing optimization on the multiplexer for phase-shift clock selection and adder delay line used in the critical path, and the optimized linearity was 0.9949 [16] and [17] use D-triggers and logic gate circuits to optimize the clock selection delay unit, which further reduces the delay deviation of the critical path. The optimized linearity is 0.994 and 0.99, respectively, but these two methods increase the circuit complexity. Although the hybrid DPWM architecture achieves higher resolution, the operation is complex, and the versatility is low, and its resolution is mainly affected by the carry chain of the second-stage adder. The delay deviation of the carry chain of the second-stage adder is greatly affected by the device, and it needs careful layout and routing to obtain better linearity.
Compared to the other methods in Table V. Although the resolution of the method proposed in this article does not reach the minimum, it has a simple structure and high reliability. The proposed method constructs the symmetric multiplexers for phase-shifted clock signals and the synchronous 2-to-1 multiplexer for selecting phase-shifted PWM signals. Then, the simple placing and routing constraints are used to compensate for critical delay paths. Achieved linearity as high as 0.99999, and the resolution deviation is smaller than other methods. The resources used in the proposed method can be obtained from other types of FPGA, which have good universality and are easy to transplant.
E. Application of Proposed Method to a DC/DC Converter
This method is applied to a 48V to 1 V/200 ADC/DC converter that powers the CPU. The technical specifications of the converter are shown in Table VI.
Since the CPU has high requirements on the volume and dynamics of the power supply, the converter is required to have very high efficiency, power density, and control bandwidth. In order to meet the power supply needs of the CPU, this paper designs a two-stage high-efficiency DC/DC converter, which consists of a DC transformer (DCX) and an interleaved buck converter. The DCX is used to achieve high-efficiency conversion from 48V to 5V, which is achieved by an LLC converter working at the resonance point with a switching frequency of 1MHz. The buck converter uses an interleaving method with a switching frequency of 1MHz to achieve high efficiency and high dynamics response. The circuit structure and control diagram of the DC/DC converter are shown in Fig. 29.
The converter test platform mainly includes input power supply, DC/DC converter, electronic load, and oscilloscope, as shown in Fig. 30. To validate the proposed high-resolution DPWM method, the steady-state and dynamic performance of the output voltage is tested.
As shown in Fig. 31, the output voltage of the DC/DC converter from 0.99V to 1.01V with DPWM single-step change. Compared with the traditional multiplexer method, the proposed method in this paper achieves better control accuracy and linearity.
The converter operates with a load of 100A, and the output voltage and current curve is as shown in Fig. 32 with proposed method.
The ADC of the DC/DC converter is LTC2311-12 with a resolution of 1mV. Considering the influence of integral non-linearity (INL), discarding the lowest bit of the ADC, its effective resolution is 2mV.
When the proposed high-resolution DPWM method is used, the single-step adjustment accuracy of the output voltage is:
$\Delta {V}_{\mathrm{O}}= 5\mathrm{\;V}\times \frac{{0.313}\mathrm{\;{ns}}}{{1000}\mathrm{\;{ns}}}= {1.565}\mathrm{\;{mV}}$
The resolution of DPWM is smaller than that of ADC, which meets the output voltage control accuracy requirements.
When the load jumps from ${50}\mathrm{\;A}$ to ${150}\mathrm{\;A}$ at a rate of ${100}\mathrm{\;A}/\mu \mathrm{s}$, the output voltage and current waveforms are shown in Fig. 33, and the voltage overshoot is ${97.5}\mathrm{{mV}}$. After the transient process is over, the output voltage runs stably around $1\mathrm{\;V}$.
The output voltage steady-state and dynamic performance test results show that the output voltage accuracy of the DC/ DC converter meets the design requirements, and the output voltage has no limit cycle oscillation. The effectiveness of the proposed method has been verified.
V. Conclusion
Less
This paper proposes the high-resolution DPWM signal modulation method based on FPGA, which uses the PLL of FPGA and the double-edge trigger function of the clock to achieve high-resolution DPWM. The logically symmetric clock multiplexers and synchronous 2-to-1 selector with simple placement and routing constraints are used to optimize the critical delay paths for high-resolution DPWM signals. The linearity of the DPWM signal is significantly improved, and the use of logic cell resources is slight. The resolution of DPWM is improved by 16 times. The power consumption of FPGA is reduced through the ALT module to disable unused phase-shift clocks. The effectiveness of this method is verified by simulation and experiment in different FPGA. The proposed architecture achieves a resolution of ${312.5}\mathrm{{ps}}$, and its maximum delay deviation is ${48.5}\mathrm{{ps}}$ with high linearity, where ${\mathrm{R}}^{2}$ is up to0.99999.
Funding
Less
  • National Natural Science Foundation of China(52177178)
  • National Natural Science Foundation of China(52127901)
  • Training Program for Excellent Young Innovators of Changsha(kq2009001)
References
Less
[1]
A. V. Peterchev S. R. Sanders . "Quantization resolution and limit cycling in digitally controlled PWM converters". in IEEE Transactions on Power Electronics, 2003. 18 (1): 301-308.
[2]
H. Peng , A. Prodic , E. Alarcon , D. Maksimovic . "Modeling of quantization effects in digitally controlled dc-dc converters". in IEEE Transactions on Power Electronics, 2007. 22 (1): 208-215.
[3]
M. G. Batarseh , W. Al-Hoor , L. Huang , C. Iannello , I. Batarseh . "Window-masked segmented digital clock manager-FPGA-based digital pulsewidth modulator technique". in IEEE Transactions on Power Electronics, 2009. 24 (11): 2649-2660.
[4]
E. F. C. Grabovski S. A. Mussa . "High resolution FPGA-based symmetrical digital pulse width modulator", in 2017 IEEE 8th International Symposium on Power Electronics for Distributed Generation Systems (PEDG), 2017. 1-5.
[5]
M. Scharrer , M. Halton , T. Scanlan . "FPGA-based digital pulse width modulator with optimized linearity", in 2009 Twenty-Fourth Annual IEEE Applied Power Electronics Conference and Exposition, 2009. 1220-1225.
[6]
S. C. Huerta , A. de Castro , O. García , J. A. Cobos . "FPGA-based digital pulse width modulator with time resolution under 2 ns". in IEEE Transactions on Power Electronics, 2008. 23 (6): 3135-3141.
[7]
A. de Castro E. Todorovich . "High resolution FPGA DPWM based on variable clock phase shifting". in IEEE Transactions on Power Electronics, 2010. 25 (5): 1115-1119.
[8]
L. S. Ge , Z. X. Chen , Z. J. Chen , Y. F. Liu . "Design and implementation of a high resolution DPWM based on a low-cost FPGA", in 2010 IEEE Energy Conversion Congress and Exposition, 2010. 2306-2311.
[9]
D. Costinett , M. Rodriguez , D. Maksimovic . "Simple digital pulse width modulator under 100 ps resolution using general-purpose FPGAs". in IEEE Transactions on Power Electronics, 2013. 28 (10): 4466-4472.
[10]
L. Salomon , R. Moreno , T. Pimenta . "Implementation of a 17 bits pulse width modulation circuit using FPGA", in 2015 27th International Conference on Microelectronics (ICM), 2015. 206-209.
[11]
X. Cheng , R. Song , G. Xie , Y. Zhang , Z. Zhang . "A new FPGA-based segmented delay-line DPWM with compensation for critical path delays". in IEEE Transactions on Power Electronics, 2018. 33 (12): 10794-10802.
[12]
Y. Furukawa , H. Nakamura , H. Eto , F. Kurokawa . "Fine resolution DPWM circuit for high frequency digital control DC-DC converter", in 2018 International Symposium on Power Electronics, Electrical Drives, Automation and Motion (SPEEDAM), 2018. 491-496.
[13]
S. Hu , J. Naiti , H. Shanshan , L. Hongtao . "FPGA-based high resolution DPWM control circuit". in Journal of Systems Engineering and Electronics, 2018. 29 (6): 1136-1141.
[14]
N. Corna , N. Lusardi , F. Garzetti , A. Geraci , M. Gustin . "Multi-channel high-resolution pulse-width modulation IP-core implementation for FPGA and SoC device", in 2019 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC), 2019. 1-3.
[15]
J. I. Morales , F. Chierchie , P. S. Mandolesi , E. E. Paolini . "All-digital high-resolution PWM with a wide duty-cycle range", in 2019 Argentine Conference on Electronics (CAE), 2019. 15-20.
[16]
C. Xin , L. Bin , H. Zhu , Y. Zhang , Z. Zhang . "A high-resolution hybrid digital pulse width modulator with dual-edge-triggered flip-flops and hardware compensation". in International Journal of Circuit Theory and Applications, 2021. 49 (1): 159-168.
[17]
X. Cheng , W. Shao , L. Xu , Y. Zhang , G. Xie , Z. Zhang . "A high resolution DPWM based on synchronous phase-shifted circuit and delay line". in IEEE Transactions on Circuits and Systems I: Regular Papers, 2020. 67 (8): 2685-2692.
[18]
M. Fernandez-Gomez , C. Fernandez , P. Zumel , A. Sanchez , A. d. Castro . "Design of DPWM with high resolution under 80 ps using low-cost Xilinx FPGA", in 2020 IEEE Applied Power Electronics Conference and Exposition (APEC), 2020. 3043-3048.
[19]
D. Sun , J. Hu , C. Wang , X. Cheng , W. Gu . "A delay-line DPWM architecture with compensation module and delay-adjustable unit based on DLL". in IEEE Transactions on Power Electronics, 2021. 36 (1): 1080-1091.
[20]
M. Fernandez-Gomez , A. Sanchez , A. de Castro , J. Lopez , P. Zumel , C. Fernandez . "Design and implementation of two hybrid high frequency DPWMs using delay blocks on FPGAs". in IEEE Transactions on Power Electronics, 2021. 36 (12): 14567-14578.
[21]
S. Arora , P. T. Balsara , D. Bhatia . "Digital pulsewidth modulation (DPWM) using direct digital synthesis". in IEEE Journal of Emerging and Selected Topics in Power Electronics, 2022. 10 (4): 4231-4244.
[22]
J. I. Morales , F. Chierchie , P. S. Mandolesi , E. E. Paolini . "Low power 18-bit PWM with 41 ps resolution in 130-nm CMOS". in IEEE Transactions on Circuits and Systems II: Express Briefs, 2022. 69 (3): 1597-1601.
[23]
T. Urkin M. M. Peretz . "Integrated delay-line based high-resolution PFM-PWM modulator", in 2023 IEEE Applied Power Electronics Conference and Exposition (APEC), 2023. 1177-1182.
Appendix
Less
Year 2024 volume 9 Issue 2
PDF
281
161
Cite this Article
BibTeX
Article Info
doi: 10.24295/CPSSTPEA.2024.00003
  • Receive Date：2023-11-17
  • Online Date：2025-07-05
  • Published：2024-06-10
Article Data
Affiliations
History
  • Received：2023-11-17
  • Revised：2024-01-12
  • Accepted：2024-02-07
Funding
National Natural Science Foundation of China(52177178)
National Natural Science Foundation of China(52127901)
Training Program for Excellent Young Innovators of Changsha(kq2009001)
Affiliations
    Hunan University College of Electrical and Information Engineering Changsha 410082 China

Corresponding:

Qianming Xu.
References
Share
https://castjournals.cast.org.cn/joweb/dldzjs/EN/10.24295/CPSSTPEA.2024.00003
Share to
QR

Scan QR to access full text

Cite this article
BibTeX
Citations
表12种不同金属材料的力学参数
科
Family		 属数
Number of
genus		 种数
Number of
species		 占总种数比例
Percentage of
total species (%)		 属
Genus		 种数
Number of
species		 占总种数比例
Percentage of total
species (%)
鹅膏菌科Amanitaceae 2 11 5.26 鹅膏菌属 Amanita 10 4.78
小菇科 Mycenaceae 2 12 5.74 丝盖伞属 Inocybe 5 2.39
多孔菌科 Polyporaceae 8 14 6.70 蜡蘑属 Laccaria 5 2.39
红菇科 Russulaceae 3 23 11.00 小皮伞属 Marasmius 6 2.87
小菇属 Mycena 11 5.26
光柄菇属 Pluteus 5 2.39
红菇属 Russula 17 8.13
栓菌属 Trametes 5 2.39
关闭全屏
  • BibTeX
  • EndNote
  • RefWorks
  • TxT
Links
Articles
Latest Articles
Most Read
Collections
Updates
Events
News
Multimedia
About
About Us
Contact
No. 86 Xueyuan South Road, Haidian District, Beijing
100081
010-62199257
qkjq@cast.org.cn

Copyright © 2025 China Association for Science and Technology. All rights reserved. For all open access content, the relevant licensing terms apply.
Sponsored by the Office of the Leading Group for Cybersecurity and Informatization of CAST, and supported by Science and Technology Review Publishing House