Digital channelization has been widely applied in the field of electronic reconnaissance. The multi-phase structure of digital channelization can reduce data rates, making it easier to implement in FPGA. However, when the number of sub-channels is large, the data rate of each sub-channel will be significantly lower than the processing rate of FPGA, resulting in a waste of FPGA resources. In this paper, we introduce two-dimensional DFT into traditional DFT digital channelization structure and propose a channelization structure that matches the processing rate of FPGA, namely the digital channelization structure based on two-dimensional DFT. This structure is verified through simulation in Matlab(Matrix Laboratory)，and its computational complexity is analyzed and compared with that of traditional DFT-based digital channelization structure. Subsequently, the FPGA implementation block diagram and FPGA resource utilization are presented, and then the structure is tested on a hardware platform. The results show that the digital channelization structure based on two-dimensional DFT can correctly perform channelization of various signals. Compared with the traditional DFT-based digital channelization structure, it reduces computational complexity and significantly improves the efficiency of FPGA resources utilization, facilitating the FPGA implementation of large-scale digital channelization, which has certain engineering significance.