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This paper investigates hardware acceleration architectures for point multiplication to address the computational efficiency issues of Koblitz curves in elliptic curve cryptography (ECC) systems. An optimized τNAF scalar conversion algorithm and its corresponding hardware structure are first proposed to reduce latency in the pre-computation phase. On this basis, two computation architectures with optimized pipeline efficiency are designed. The area-efficient architecture employs a compact four-stage pipeline with a single multiplier to improve hardware resource utilization. For different binary fields (GF(2163), GF(2283), and GF(2571)), the low-latency architecture adopts two-stage and three-stage pipeline designs respectively, and leverages dual parallel multipliers to reduce the clock cycles required for point addition. Experimental results on the Virtex-7 FPGA platform demonstrate that both architectures achieve substantial latency improvements across all three fields. Compared with state-of-the-art designs, the area-efficient architecture reduces latency by 58.111% over GF(2571), while the low-latency architecture reduces latency by 43.952% over GF(2163). The results demonstrate that optimizing pipeline scheduling and algorithm mapping can effectively balance the computational performance and resource consumption of ECC coprocessors, providing a practical reference for the design of high-performance cryptographic hardware.
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| 科 Family | 属数 Number of genus | 种数 Number of species | 占总种数比例 Percentage of total species (%) | 属 Genus | 种数 Number of species | 占总种数比例 Percentage of total species (%) |
|---|---|---|---|---|---|---|
| 鹅膏菌科Amanitaceae | 2 | 11 | 5.26 | 鹅膏菌属 Amanita | 10 | 4.78 |
| 小菇科 Mycenaceae | 2 | 12 | 5.74 | 丝盖伞属 Inocybe | 5 | 2.39 |
| 多孔菌科 Polyporaceae | 8 | 14 | 6.70 | 蜡蘑属 Laccaria | 5 | 2.39 |
| 红菇科 Russulaceae | 3 | 23 | 11.00 | 小皮伞属 Marasmius | 6 | 2.87 |
| 小菇属 Mycena | 11 | 5.26 | ||||
| 光柄菇属 Pluteus | 5 | 2.39 | ||||
| 红菇属 Russula | 17 | 8.13 | ||||
| 栓菌属 Trametes | 5 | 2.39 |
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