An embedded feedforward ripple cancellation (EFFRC) technology with a low-pass filter is proposed to address the issue of poor power supply rejection (PSR) performance in traditional output-capacitorless low-dropout regulator (LDO) operating in the medium and high frequency range. Firstly, an adaptive bias super source follower is inserted into a cascaded flipped voltage followers to drive the power transistor, and Miller compensation and feedforward capacitance compensation techniques are employed to ensure system stability and widen the LDO loop bandwidth. Additionally, a dedicated low-pass filter is integrated into the buffer to effectively eliminate power ripples at the LDO output without consuming additional power, thereby significantly enhancing PSR frequency characteristics. The designed LDO is implemented using SMIC130 nm CMOS process. Simulation results demonstrate that it achieves a low-frequency PSR value of 90 dB across a load change ranging from 0 to 50 mA. Furthermore, the PSR exhibits a frequency bandwidth exceeding 10 MHz, with potential improvements of up to 12 dB in the mid-frequency band. The good PSR characteristics show that the LDO has good dynamic suppression ability for different-frequency noise of input voltage, so it can provide a clean power supply voltage for the circuit driven by it, such as high-performance analog-to-digital converters and low-noise amplifier.