Traditional CLLLC resonant converters do not effectively utilize the switching tubes of the rectifier circuit during operation, resulting in current flowing only through their anti-parallel diodes, leading to high losses and low efficiency. The traditional synchronous rectification scheme based on drain-source voltage is susceptible to the influence of parasitic inductance of switching tubes at high frequencies, which affects the efficiency of synchronous rectification. A detailed analysis of the impact of parasitic parameters on the duty cycle and efficiency of synchronous rectification in CLLLC resonant converters is provided, and an optimization strategy for synchronous rectification based on drain-source voltage is proposed. In a CLLLC resonant converter, the strategy adjusts the turn-off threshold voltage of secondary MOSFET, and improves the efficiency of synchronous rectification by compensating the duty cycle loss time of the synchronous rectifier switching tubes. The experimental results show that the synchronous rectification optimization strategy proposed can effectively reduce the duty cycle loss caused by parasitic parameters and lower the overall losses of CLLLC resonant converter, compared with the traditional synchronous rectification strategy based on drain-source voltage.