As the master control computer of the Platform Inertial Navigation System (PINS) constitutes a hard real-time multicore embedded system, its control cycle directly impacts navigation accuracy. To address the issues of low resource utilization and constrained computing frequency resulting from the bin-packing problem inherent in traditional centralized partitioned scheduling, the Self-Correcting Longest-Path DAG Scheduling Algorithm (SLS) is proposed. The algorithm employs directed acyclic graphs (DAGs) to model complex inertial navigation tasks with precedence constraints, constructing a two-stage closed-loop framework of "static planning and dynamic correction". In the static phase, parallel tasks are greedily allocated across multiple cores based on longest-path priorities. The dynamic phase introduces a self-correcting mechanism that utilizes a weighted averaging method to continuously refine node execution time estimates, thereby mitigating the cumulative degradation of scheduling performance caused by worst-case execution time (WCET) estimation errors. Hardware-in-the-loop simulation experiments demonstrate that, compared with recent state-of-the-art algorithms in the inertial navigation field, the SLS algorithm significantly reduces task execution time, enhances multicore resource utilization and load balancing, and effectively improves the system accuracy and real-time performance of PINS.