To address the challenges of excessive resource demands and difficulty in meeting low-power requirements in the embedded domain when field programmable gate array (FPGA) are utilized to accelerate convolution operations, a resource-efficient FPGA-based convolution acceleration method for binary neural networks (BNN) is proposed. First, the computational characteristics and resource consumption patterns of various parallelization schemes during the forward inference process of the convolution layer are systematically analyzed. Leveraging the lowbit-width feature of BNN, a high dimensional data splicing and dimensionality reduction storage scheme is introduced. Subsequently, a channel dimension reduction rotation cache (CDR) structure tailored for BNN is proposed, aiming to achieve the combined benefits of intra-convolution kernel parallelism and inter-feature map parallelism with moderate cache bandwidth expansion. Furthermore, to fully exploit the performance advantages of the CDR structure, a specialized CDR processing unit is designed, and the adder tree structure is optimized. The processing unit supports flexible adjustment of different pipeline levels and can achieve higher-level parallel computing capabilities through a repeated invocation mechanism, adapting to diverse system requirements. Experimental results demonstrate that the BNN accelerator based on the CDR architecture achieves significantly superior computational density and storage density compared to existing state-of-the-art solutions when deployed on the Xilinx XC7Z020 chip. It also exhibits low-power characteristics and enables faster inference speed，making it well-suited for resource-and power constrained embedded platforms.