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Targeting the future demand for high computing power chips, this paper analyzes the development trends of high computing power chips in China and abroad and further presents an expression of the computing power of a chip involving data interconnection, computing power per transistor, transistor density per unit area, and chip area. It then describes the key technologies for the future development of high computing power chips and explains how these technologies make a difference in accordance with the proposed expression of computing power. Specifically, the current status of these technologies, including advanced integrated circuit manufacturing, monolithic three-dimensional integration, domain-specific architectures, coarse-grained reconfigurable architecture (CGRA), in-memory computing (IMC), chiplets, and wafer-scale integration, in China and abroad and their performance in elevating the computing power of chips are discussed from the perspectives of new materials, new devices, advanced processes, novel architectures, and integrated packaging. The prospects of these technologies and the challenges they face are examined in depth. Regarding the current situation of high computing power chips in China and the restrictions on the development of advanced integrated circuit manufacturing processes, this paper proposes proceeding from the perspective of “architecture + integration + system” to explore an integrated, independently controllable, and innovative approach to high computing power chips. Mature manufacturing processes and novel architectures of CGRA and IMC, together with chiplets based on advanced integration, can be leveraged to achieve breakthroughs in total computing power.
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面向未来高算力芯片需求,分析了国内外高算力芯片发展趋势,提出由数据互连、单位晶体管提供的算力、晶体管密度和芯片面积构成的芯片算力表达式。介绍了未来高算力芯片发展的关键技术,并结合算力表达式论述相关技术如何发挥作用。从新材料、新器件、先进工艺、新架构、集成封装等角度出发,探讨了集成电路先进制造工艺、单片三维集成技术、领域专用架构、粗粒度可重构架构、存算一体技术、芯粒（Chiplet）技术和晶圆级集成等国内外发展现状及其对芯片算力的提升效果,并深入分析了各项技术的发展和挑战。结合中国高算力芯片现状和集成电路先进制程发展受限,提出从“架构+集成+系统”出发,探索实现高算力芯片的一体化自主可控创新路径,可以采用成熟制程,结合粗粒度可重构和存算一体新型架构,采用基于先进集成的芯粒技术实现总算力突破。
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 |
姚鹏,助理研究员。研究方向为忆阻器阵列及其应用,存算一体宏电路设计,存算一体AI芯片架构和算法等。在Nature、Nature Communications等学术期刊和ISSCC、IEDM、VLSI等学术会议上发表多篇论文。电子信箱： yaop14@tsinghua.org.cn。 |
 |
吴华强,教授,博士研究生导师。现任清华大学集成电路学院院长。国家杰出青年科学基金获得者。长期从事新型存储器与存算一体技术研究,并开展了从系统、电路到器件的多层次创新研究。先后负责国家自然科学基金、国家“863”计划、国家“973”计划、国家科技重大专项、国家重点研发计划等国家重大科技任务40余项。2021年入选“全球顶尖前10万科学家”榜单。获首届“科学探索奖”。在Nature、Nature Electronics等学术期刊和ISSCC、IEDM等学术会议上发表论文100余篇。电子信箱： wuhq@tsinghua.edu.cn。 |
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姚鹏,助理研究员。研究方向为忆阻器阵列及其应用,存算一体宏电路设计,存算一体AI芯片架构和算法等。在Nature、Nature Communications等学术期刊和ISSCC、IEDM、VLSI等学术会议上发表多篇论文。电子信箱： yaop14@tsinghua.org.cn。
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姚鹏,助理研究员。研究方向为忆阻器阵列及其应用,存算一体宏电路设计,存算一体AI芯片架构和算法等。在Nature、Nature Communications等学术期刊和ISSCC、IEDM、VLSI等学术会议上发表多篇论文。电子信箱： yaop14@tsinghua.org.cn。
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吴华强,教授,博士研究生导师。现任清华大学集成电路学院院长。国家杰出青年科学基金获得者。长期从事新型存储器与存算一体技术研究,并开展了从系统、电路到器件的多层次创新研究。先后负责国家自然科学基金、国家“863”计划、国家“973”计划、国家科技重大专项、国家重点研发计划等国家重大科技任务40余项。2021年入选“全球顶尖前10万科学家”榜单。获首届“科学探索奖”。在Nature、Nature Electronics等学术期刊和ISSCC、IEDM等学术会议上发表论文100余篇。电子信箱： wuhq@tsinghua.edu.cn。
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吴华强,教授,博士研究生导师。现任清华大学集成电路学院院长。国家杰出青年科学基金获得者。长期从事新型存储器与存算一体技术研究,并开展了从系统、电路到器件的多层次创新研究。先后负责国家自然科学基金、国家“863”计划、国家“973”计划、国家科技重大专项、国家重点研发计划等国家重大科技任务40余项。2021年入选“全球顶尖前10万科学家”榜单。获首届“科学探索奖”。在Nature、Nature Electronics等学术期刊和ISSCC、IEDM等学术会议上发表论文100余篇。电子信箱： wuhq@tsinghua.edu.cn。
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| 代工厂 | 国家/地区 | 量产工艺节点/nm | 晶体管密度/（106 • mm-2） |
| 台积电 | 中国台湾 | 5 | 196.6 |
| 中芯国际 | 中国大陆 | 14 | 30.0 |
| 英特尔 | 美国 | 7 | 106.1 |
| 三星 | 韩国 | 5 | 145.7 |
), ArticleFig(id=1241718678174102459, tenantId=1146029695717560320, journalId=1146032081894723586, articleId=1241718639385178956, language=CN, label=表1, caption=
全球主要集成电路制造厂的量产工艺节点及晶体管密度
, figureFileSmall=null, figureFileBig=null, tableContent=
| 代工厂 | 国家/地区 | 量产工艺节点/nm | 晶体管密度/（106 • mm-2） |
| 台积电 | 中国台湾 | 5 | 196.6 |
| 中芯国际 | 中国大陆 | 14 | 30.0 |
| 英特尔 | 美国 | 7 | 106.1 |
| 三星 | 韩国 | 5 | 145.7 |
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