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Article(id=1193556933148898241, tenantId=1146029695717560320, journalId=1149653034449285133, issueId=1193556932167431095, articleNumber=null, orderNo=null, doi=10.16790/j.cnki.1009-9239.im.2025.04.011, pmid=null, cstr=null, oa=null, hot=null, price=null, onlineType=0, articleFormat=0, articleType=null, articleTypeStr=research-article, receivedDate=1713542400000, receivedDateStr=2024-04-20, revisedDate=1717776000000, revisedDateStr=2024-06-08, acceptedDate=null, acceptedDateStr=null, onlineDate=1762495748078, onlineDateStr=2025-11-07, pubDate=1745078400000, pubDateStr=2025-04-20, doiRegisterDate=null, doiRegisterDateStr=null, onlineIssueDate=1762495748078, onlineIssueDateStr=2025-11-07, onlineJustAcceptDate=null, onlineJustAcceptDateStr=null, onlineFirstDate=null, onlineFirstDateStr=null, sourceXml=null, magXml=null, createTime=1762495748078, creator=13701087609, updateTime=1762495748078, updator=13701087609, issue=Issue{id=1193556932167431095, tenantId=1146029695717560320, journalId=1149653034449285133, year='2025', volume='58', issue='4', pageStart='1', pageEnd='144', issueExtLink='null', onlineDate='null', pubDate='null', beforeIssueId=null, nextIssueId=null, price=null, status=1, issueComplete=1, articleOrder=1, issueType=-1, specialIssue=null, createTime=1762495747843, creator=13701087609, updateTime=1762498255746, updator=13701087609, preIssue=null, nextIssue=null, ext={EN=IssueExt(id=1193567451108573868, tenantId=1146029695717560320, journalId=1149653034449285133, issueId=1193556932167431095, language=EN, specialIssueTitle=, coverIllustrator=null, specialIssueEditor=, specialIssueAbout=), CN=IssueExt(id=1193567451112768173, tenantId=1146029695717560320, journalId=1149653034449285133, issueId=1193556932167431095, language=CN, specialIssueTitle=, coverIllustrator=null, specialIssueEditor=, specialIssueAbout=)}, issueFiles=null}, startPage=82, endPage=89, ext={EN=ArticleExt(id=1193556933358613444, articleId=1193556933148898241, tenantId=1146029695717560320, journalId=1149653034449285133, language=EN, title=Effect of plasma silicon deposition on XLPE/SIR interface discharge, columnId=1190369198472794288, journalTitle=Insulating Materials, columnName=Insulation Technology, runingTitle=null, highlight=null, articleAbstract=

Interfacial discharge between XLPE and SIR in cable joints is one of the main causes of cable failure. In order to improve this phenomenon, the XLPE sample surface was treated by plasma silicon deposition with different time, and the micro-morphology and interface discharge tests were carried out. The results show that the plasma silicon deposition technology can effectively improve the voltage resistance of XLPE/SIR interface. With the increase of plasma silicon deposition treatment time, the surface roughness of XLPE sample decreases at first and then increases, and its change trend is the same as that of the initial discharge voltage, breakdown voltage, and voltage increase amplitude of XLPE/SIR interface, and is opposite to that of the surface resistivity. The XLPE sample after 3 min of plasma silicon deposition has the smallest surface roughness (R a=41.8nm) and the largest surface resistivity (857×1012 Ω). Under this treatment time, the XLPE/SIR interface has the largest actual contact area, the fewest micro-pores, and the largest increase in breakdown voltage. Among them, the breakdown voltage increases by 66.7% compared with the untreated XLPE/SIR interface.

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电缆接头的交联聚乙烯（XLPE）与硅橡胶（SIR）界面发生放电是导致电缆故障的主要原因之一。为改善这一现象，本文对XLPE样片表面进行不同时间等离子体硅沉积处理，并对其进行微观形貌测试和界面放电实验。结果表明：等离子体硅沉积技术能有效提高XLPE/SIR界面的耐压性能。随着等离子体硅沉积处理时间的增加，XLPE样片表面粗糙度先减小后增大，其变化趋势与XLPE/SIR界面的起始放电电压、击穿电压和升压幅值的变化趋势相同，与表面电阻率的变化趋势相反。其中，处理时间为3 min的XLPE样片具有最小的表面粗糙度（R a=41.8 nm）和最大的表面电阻率（857×1012 Ω）。在该处理时间下，XLPE/SIR界面的实际接触面积最大、界面的微孔隙数量最少、击穿电压提升幅度最大，其中击穿电压相对于未处理XLPE/SIR界面提升了66.7%。

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谢庆（1979-），男（汉族），四川广元人，教授，博士，主要从事高电压与绝缘技术方面的研究。
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燕一博（2000-），男（汉族），河南商丘人，硕士生，主要从事高电压与绝缘技术方面的研究。

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燕一博（2000-），男（汉族），河南商丘人，硕士生，主要从事高电压与绝缘技术方面的研究。

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燕一博（2000-），男（汉族），河南商丘人，硕士生，主要从事高电压与绝缘技术方面的研究。

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Surface modification of epoxy using an atmospheric pressure dielectric barrier discharge to accelerate surface charge dissipation[J].IEEE Transactions on Dielectrics and Electrical Insulation,2017,24(3):1557-1565., articleTitle=Surface modification of epoxy using an atmospheric pressure dielectric barrier discharge to accelerate surface charge dissipation, refAbstract=null)], funds=[Fund(id=1195072315533824063, tenantId=1146029695717560320, journalId=1149653034449285133, articleId=1193556933148898241, awardId=52277147, language=CN, fundingSource=国家自然科学基金资助项目(52277147), fundOrder=null, country=null), Fund(id=1195072315588350016, tenantId=1146029695717560320, journalId=1149653034449285133, articleId=1193556933148898241, awardId=3222057, language=CN, fundingSource=北京市自然科学基金资助项目(3222057), fundOrder=null, country=null), Fund(id=1195072315647070273, tenantId=1146029695717560320, journalId=1149653034449285133, articleId=1193556933148898241, awardId=2023M741322, language=CN, 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处理时间/min 起始放电电压 击穿电压 升压幅值
0 5.7 9.6 3.9
1 6.5 10.6 4.1
2 6.7 13.5 6.8
3 7.6 16.0 8.4
4 7.2 15.2 8.0
5 6.8 13.8 7.0
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不同处理时间XLPE/SIR界面的局部放电测试结果

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处理时间/min 起始放电电压 击穿电压 升压幅值
0 5.7 9.6 3.9
1 6.5 10.6 4.1
2 6.7 13.5 6.8
3 7.6 16.0 8.4
4 7.2 15.2 8.0
5 6.8 13.8 7.0
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处理时间/min C O Si
0 88.9 6.6 4.5
1 84.7 8.6 6.7
2 75.7 13.8 10.4
3 70.6 16.0 13.4
4 65.2 17.2 17.6
5 50.9 20.7 28.4
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不同处理时间XLPE样片表面主要元素的相对含量

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处理时间/min C O Si
0 88.9 6.6 4.5
1 84.7 8.6 6.7
2 75.7 13.8 10.4
3 70.6 16.0 13.4
4 65.2 17.2 17.6
5 50.9 20.7 28.4
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等离子体硅沉积对XLPE/SIR界面放电的影响研究
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燕一博 1 , 夏国巍 1 , 段祺君 2 , 骆立衡 1 , 尹国华 1 , 谢庆 1
绝缘材料 | 绝缘技术 2025,58(4): 82-89
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绝缘材料 | 绝缘技术 2025, 58(4): 82-89
等离子体硅沉积对XLPE/SIR界面放电的影响研究
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燕一博1, 夏国巍1, 段祺君2, 骆立衡1, 尹国华1, 谢庆1
作者信息
  • 1 华北电力大学 新能源电力系统国家重点实验室，河北 保定 071003
  • 2 北京智慧能源研究院，北京 102209

    • 燕一博（2000-），男（汉族），河南商丘人，硕士生，主要从事高电压与绝缘技术方面的研究。

通讯作者:

谢庆（1979-），男（汉族），四川广元人，教授，博士，主要从事高电压与绝缘技术方面的研究。
Effect of plasma silicon deposition on XLPE/SIR interface discharge
Yibo YAN1, Guowei XIA1, Qijun DUAN2, Liheng LUO1, Guohua YIN1, Qing XIE1
Affiliations
  • 1 State Key Laboratory of Alternate Electrical Power System with Renewable Energy Sources, North China Electric Power University, Baoding 071003, China
  • 2 Beijing Smart Energy Research Institute, Beijing 102209, China
出版时间: 2025-04-20 doi: 10.16790/j.cnki.1009-9239.im.2025.04.011
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摘要
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电缆接头的交联聚乙烯（XLPE）与硅橡胶（SIR）界面发生放电是导致电缆故障的主要原因之一。为改善这一现象，本文对XLPE样片表面进行不同时间等离子体硅沉积处理，并对其进行微观形貌测试和界面放电实验。结果表明：等离子体硅沉积技术能有效提高XLPE/SIR界面的耐压性能。随着等离子体硅沉积处理时间的增加，XLPE样片表面粗糙度先减小后增大，其变化趋势与XLPE/SIR界面的起始放电电压、击穿电压和升压幅值的变化趋势相同，与表面电阻率的变化趋势相反。其中，处理时间为3 min的XLPE样片具有最小的表面粗糙度（R a=41.8 nm）和最大的表面电阻率（857×1012 Ω）。在该处理时间下，XLPE/SIR界面的实际接触面积最大、界面的微孔隙数量最少、击穿电压提升幅度最大，其中击穿电压相对于未处理XLPE/SIR界面提升了66.7%。

等离子体硅沉积  /  交联聚乙烯  /  硅橡胶  /  界面放电  /  表面粗糙度

Interfacial discharge between XLPE and SIR in cable joints is one of the main causes of cable failure. In order to improve this phenomenon, the XLPE sample surface was treated by plasma silicon deposition with different time, and the micro-morphology and interface discharge tests were carried out. The results show that the plasma silicon deposition technology can effectively improve the voltage resistance of XLPE/SIR interface. With the increase of plasma silicon deposition treatment time, the surface roughness of XLPE sample decreases at first and then increases, and its change trend is the same as that of the initial discharge voltage, breakdown voltage, and voltage increase amplitude of XLPE/SIR interface, and is opposite to that of the surface resistivity. The XLPE sample after 3 min of plasma silicon deposition has the smallest surface roughness (R a=41.8nm) and the largest surface resistivity (857×1012 Ω). Under this treatment time, the XLPE/SIR interface has the largest actual contact area, the fewest micro-pores, and the largest increase in breakdown voltage. Among them, the breakdown voltage increases by 66.7% compared with the untreated XLPE/SIR interface.

plasma silicon deposition  /  crosslinked polyethylene  /  silicone rubber  /  interfacial discharge  /  surface roughness
燕一博, 夏国巍, 段祺君, 骆立衡, 尹国华, 谢庆. 等离子体硅沉积对XLPE/SIR界面放电的影响研究. 绝缘材料, 2025 , 58 (4) : 82 -89 . DOI: 10.16790/j.cnki.1009-9239.im.2025.04.011
Yibo YAN, Guowei XIA, Qijun DUAN, Liheng LUO, Guohua YIN, Qing XIE. Effect of plasma silicon deposition on XLPE/SIR interface discharge[J]. Insulating Materials, 2025 , 58 (4) : 82 -89 . DOI: 10.16790/j.cnki.1009-9239.im.2025.04.011
正文
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0 引言
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高压电缆由于其良好的绝缘性能和可靠性，已广泛应用于输电领域。然而受生产工艺和运输条件限制，单根电缆的长度无法满足输电需求，导致安装时需通过接头连接多段电缆。电缆接头内部容易产生电荷积聚，这增加了绝缘故障发生风险的概率[1-4]。电缆接头处主绝缘交联聚乙烯（XLPE）和增强绝缘硅橡胶（SIR）间由于材料性能存在差异[5-6]，在两种材料界面处容易积累空间电荷，从而导致电场畸变并发生放电事故[7-9]。据统计，电缆接头处的界面放电是导致电缆故障的主要原因之一[10]，因此改善XLPE/SIR复合界面的局部放电现象至关重要。
为了改善XLPE/SIR复合界面处局部放电的情况，研究人员进行了大量探索。研究表明，XLPE/SIR界面的特性取决于很多方面，比如表面粗糙度、电缆接头密封性、温度和运行环境等[11-14]。张世泽等[15]采用激光剥离技术来降低XLPE电缆表面的粗糙度，提高了电缆绝缘层的界面绝缘性能。古亮[16]采用不同类型的砂纸对聚乙烯（PE）进行打磨，发现PE表面粗糙度越高，PE/SIR界面的起始放电电压越小。邹林等[17]通过施加一定的界面压强模拟电缆附件中的界面压强，研究不同界面压强和不同表面粗糙度的PE对PE/SIR界面局部放电特性的影响，结果表明PE表面越粗糙，局部放电起始电压越小；随着界面压强的增大，PE/SIR界面的局部放电起始电压增大，局部放电量逐渐减小，总放电次数也减小。柳松等[18]测量分析了XLPE/SIR界面涂覆两种不同硅脂，在不同粗糙度的交流及冲击电压下的击穿特性，结果表明XLPE/SIR界面的光滑程度越高，界面的击穿电压值越大。尽管上述技术取得了显著成效，但由于存在处理周期长、操作复杂以及设备成本高等问题，大规模应用于工业生产中仍面临挑战。等离子体技术因操作方便、设备简单、效率高和环境友好等特点，近几年来成为了材料改性领域的研究热点[19-20]；而硅沉积技术具备提供低温沉积、高质量薄膜、快速沉积速率、薄膜均匀性、环境友好、广泛的应用范围和可控性强等优点，成为等离子体技术的常用方法之一。C D SEOK等[21]研究发现，等离子体硅沉积梯度改性可使环氧树脂（EP）不同区域的表面电导率实现梯度分布，改性后的样品表面变得更加光滑。
本文采用等离子体硅沉积技术对XLPE表面进行改性处理，并调控XLPE表面粗糙度和表面电阻率。在XLPE表面分别进行不同时间的等离子体硅沉积，并测试XLPE表面的微观形貌以及XLPE/SIR界面的起始放电电压、击穿电压和最大放电量，研究等离子体硅沉积处理时间（简称等离子体处理时间）对XLPE/SIR界面放电的影响。
1 实验
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1.1 XLPE样片的制备
先将热压成型机（型号为XLB-D，青岛锦九洲橡胶机械有限公司）的温度设置为170℃，然后将铺上XLPE颗粒的模具平放在热压成型机的下板中央进行预热，等热压成型机的温度升至170℃后再保持10 min，此时XLPE颗粒已经熔化。保持温度为170℃，按照5 MPa/5 min+10 MPa/5 min+15 MPa/ 5 min的程序进行热压，最终制得XLPE样片。
1.2 等离子体硅沉积XLPE样片
应用图1所示的实验平台进行等离子体硅沉积实验。首先将制备好的XLPE样片放置在真空干燥箱中干燥12 h；然后取出干燥后的XLPE样片置于DBD反应釜正中心，盖上石英玻璃并调节放电电极。设置水浴加热锅温度为70℃，将盛放TEOS的洗气瓶放入水浴加热锅加热5 min后打开两路Ar气，通过质量流量计将直接通入反应釜的一路Ar气流速设置为2.5 mL/s，与洗气瓶相连的一路Ar气流速设置为0.4 mL/s。先将混合气体通入反应釜 1 min，之后排出反应釜内的空气。设置电源电压为7 kV，电源频率为60 kHz，然后对XLPE样片进行不同时间的等离子体硅沉积。
1.3 XLPE/SIR界面耐压试验
实验中电缆接头的模型从上到下由有机玻璃上盖板、XLPE样片、铜电极、SIR样片、有机玻璃下盖板和螺母组成。将铜电极置于XLPE和SIR两个样片的中间位置，并保证两个铜电极的尖端距离为1 cm。
按照图2所示的电路图搭建好整个实验放电回路，在打开开关之前检查整条电路的通断情况。打开调压器和变压器开关后，缓慢按下升压按钮进行升压，当听到试样平板产生强烈的电晕声时，立刻降低加压的速度，通过分压器记录此时的起始放电电压并通过采集卡对局放信号进行采集和分析。当加压至整个XLPE/SIR界面处发生击穿时，记录试样的击穿电压。发生击穿后迅速按下降压键将电压降至0，然后关闭调压器开关。
1.4 XLPE表面电荷消散速率测试
基于等温表面电流衰减（isothermal surface potential decay，ISPD）法对不同试样进行表面电荷消散速率测试，表面电荷消散实验平台如图3所示。首先开启静电电位计，打开电脑上的数据采集软件，利用针电极施加7 kV直流电压对XLPE样片表面进行1 min电晕充电。将有源电容探头置于样片上方2 mm处，用静电探头对准XLPE样片的充电位置并将数据采集软件上的采集频率设置为10 Hz，采集30 min内XLPE样片的表面电位数据。采样完成后关闭采集软件和静电探头，并更换新样片重复上述步骤。将实验数据用程序进行归一化处理得到试样的表面电位衰减曲线，最后根据处理后的数据计算出所有样片的陷阱能级分布曲线。
2 实验结果
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2.1 局部放电测试结果
随着等离子体处理时间存在差异的增加，不同XLPE/SIR界面放电情况。将XLPE/SIR试样放在局部放电电路进行放电实验，利用采集卡记录处理时间为0、1、2、3、4、5 min的等离子体改性XLPE/SIR界面的起始放电电压和击穿电压，测试结果如表1所示，每种试样取5组结果的平均值进行记录。
从表1可以看出，随着等离子体处理时间的增加，XLPE/SIR界面的起始放电电压、击穿电压和升压幅值（击穿电压与起始放电电压的差值）都呈现出先增大后减小的趋势。升压幅值越大，XLPE/SIR界面耐受的电压范围越大。其中处理时间为3 min 的XLPE/SIR界面起始放电电压、击穿电压和升压幅值均达到最大，其击穿电压相对于未处理XLPE/SIR界面提升了66.7%，达到最大的提升效果，从而能够有效地减少界面放电次数。
为了验证研究XLPE/SIR界面的最大放电量和放电次数，进一步测试了样片的PRPT谱图，结果如图4所示。谱图的纵坐标代表放电量，谱图上的小点个数代表放电次数。从图4可以看出，XLPE/SIR界面的最大放电量随等离子体处理时间的增加呈现出先减小后增大的趋势。未处理的XLPE/SIR界面最大放电量达到660.0 pC，而经过3 min处理后的XLPE/SIR界面的最大放电量减小至364.7 pC。处理时间为2 min和3 min的XLPE/SIR界面放电次数远小于其他处理时间的XLPE/SIR界面放电次数。
2.2 XLPE样片表面SEM测试
为了更好地观察等离子体硅沉积技术对XLPE样片表面的影响，对不同等离子体处理时间的XLPE样片表面进行SEM测试，结果如图5所示。
从图5可以看出，未处理的XLPE样片表面有少量颗粒物分布，表面整体比较光滑。处理时间为1 min和2 min的XLPE样片表面出现了大量颗粒物。随着处理时间的增加，XLPE样片表面的颗粒物发生团聚并聚集成大的颗粒物，其中处理时间为5 min的XLPE样片表面团聚现象最严重。
图6为不同等离子体处理时间XLPE样片的EDS图像，其中紫色部分为Si元素。从图6可以看出，处理时间为3 min的XLPE样片表面Si元素分布最均匀，随着处理时间增加，紫色部分开始聚集，样片表面沉积的硅氧薄膜面积越来越大。
表2为XLPE样片表面相对元素含量随等离子体处理时间的变化规律。从表2可以看出，随着等离子体处理时间的增加，XLPE样片表面元素的相对含量也发生显著变化。其中，C元素的相对含量逐渐降低，Si和O元素的相对含量不断升高。分析认为，这是因为在进行等离子体硅沉积处理时，TEOS在高能等离子体作用下，生成了大量的Si-O-Si官能团，最终形成薄膜沉积在XLPE样片表面。
2.3 XLPE表面电荷消散和陷阱分布特性
不同等离子体处理时间的XLPE表面电位衰减曲线如图7所示。
从图7可以看出，未经过等离子体处理的XLPE表面电荷消散速率相对较快，在衰减时间为1 800 s时的表面电位为其初始电位的60%。随着等离子体处理时间的增加，在处理时间为1～3 min时，XLPE样片表面电荷的消散速率开始逐渐下降，处理时间为3 min的XLPE样片表面电荷消散速率达到最小，在衰减时间为1 800 s时其表面电位衰减到初始电位的88%。在处理时间为3～5 min时，XLPE样片表面电荷的消散速率开始急剧上升，处理时间为5 min的XLPE样片表面电荷消散速率最大。
不同等离子体处理时间的XLPE样片表面陷阱分布曲线如图8所示。从图8可以看出，随着等离子体处理时间的增加，XLPE样片表面深陷阱能级密度先增大后减小，且改性后一部分样片出现了浅陷阱。从处理时间上来看，处理时间为0～3 min的XLPE样片表面陷阱能级深度稍微上升；但处理时间为3～5 min的XLPE样片表面浅陷阱开始逐渐上升且深陷阱密度开始逐渐下降，部分深陷阱转变成了浅陷阱，这是因为等离子体处理引入的能量和活性粒子改变了样片表面的化学结构，导致深陷阱能及被破坏或重组，形成更多浅陷阱。其中处理时间为5 min的XLPE样片表面的深陷阱密度最小，浅陷阱密度最大。
3 分析与讨论
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3.1 XLPE样片表面粗糙度测试
为了分析等离子体处理时间对XLPE样片表面粗糙度的影响，对不同处理时间的XLPE样片表面粗糙度进行测试，结果如图9所示。从图9可以看出，随着等离子体处理时间的增加，XLPE样片表面的粗糙度呈现先减小后增大的趋势。等离子体硅沉积技术通过在XLPE表面镀上一层薄膜来改变其表面粗糙度，XLPE表面新形成的薄膜能够覆盖XLPE表面原有的缺陷。为了能够表征XLPE表面的粗糙度，计算了不同等离子处理时间XLPE样片的表面粗糙度R a，结果如图10所示。从图10可以看出，XLPE样片的表面粗糙度R a随着等离子体处理时间的增加先减小后增大，R a的变化范围为41.8～78.9 nm。R a在处理时间为0～3 min时一直呈现减小的趋势，其中处理时间为3 min的XLPE样片表面粗糙度R a最小（41.8 nm）；处理时间为3～5 min时，XLPE样片的表面粗糙度R a开始上升。虽然等离子体硅沉积能在XLPE表面镀上一层薄膜掩盖其表面原有的缺陷，但是随着等离子体处理时间的增加，沉积在XLPE表面的薄膜也变得越来越不均匀，反而会促进XLPE/SIR界面放电。
XLPE/SIR界面处存在的微孔隙增强了电荷运输，容易导致界面放电[22]。XLPE和SIR的实际接触面积远小于XLPE样片的真实面积，这是因为XLPE/SIR界面之间存在大量的微孔隙，XLPE和SIR的实际接触面积和界面的形貌密切相关，界面形貌又与界面粗糙度密切相关。随着XLPE样片表面粗糙度的降低，XLPE/SIR界面处的微孔隙数量减少，使得XLPE/SIR界面的实际接触面积增大，起始放电电压和击穿电压也随之增大。
3.2 XLPE样片表面电阻率测试
为了进一步研究等离子硅沉积技术对XLPE/SIR界面耐压性能的影响机理，对不同处理时间的XLPE样片进行表面电阻率测试，结果如图11所示。从图11可以看出，未处理的XLPE样片表面电阻率为758×1012 Ω，随着等离子体处理时间的增加，XLPE样片的表面电阻率呈现先增大后减小的趋势。其中处理时间为3 min的XLPE样片表面电阻率最大，达到857×1012 Ω，处理时间为5 min的XLPE样片表面电阻率减小至799×1012 Ω。
XLPE样片表面电阻率的变化趋势与表面粗糙度的变化趋势呈负相关，这是由于XLPE样片表面比较粗糙，表面缺陷较多，粗糙的表面会吸收更多的空气和水蒸气，导致表面变得潮湿，从而降低了XLPE样片的表面电阻率。
4 结论
收起
（1）等离子体硅沉积处理技术能在XLPE样片表面沉积一层薄膜，改变XLPE样片表面的元素含量、表面粗糙度、陷阱分布和表面电阻率。
（2）随着等离子体处理时间的增加，XLPE/SIR界面的起始放电电压、击穿电压和升压幅值均呈先升高后下降的趋势；XLPE样片表面粗糙度的变化趋势为先减小后增大。其中处理时间为3 min的XLPE样片表面粗糙度最小，表面电阻率最大，XLPE/SIR界面的击穿电压相对于未处理的XLPE/SIR界面提升了66.7%，达到最大的提升效果，。
（3）等离子体硅沉积处理技术降低了XLPE表面粗糙度并增大了其表面电阻率，使XLPE/SIR界面的实际接触面积变大、界面的微孔隙数量减少，从而抑制电荷在界面微孔隙处产生积聚，最终抑制了XLPE/SIR界面放电。
基金
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  • 国家自然科学基金资助项目(52277147)
  • 北京市自然科学基金资助项目(3222057)
  • 中国博士后科学基金资助项目(2023M741322)
文献
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2025年第58卷第4期
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doi: 10.16790/j.cnki.1009-9239.im.2025.04.011
  • 接收时间：2024-04-20
  • 首发时间：2025-11-07
  • 出版时间：2025-04-20
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  • 收稿日期：2024-04-20
  • 修回日期：2024-06-08
基金
国家自然科学基金资助项目(52277147)
北京市自然科学基金资助项目(3222057)
中国博士后科学基金资助项目(2023M741322)
作者信息
    1 华北电力大学 新能源电力系统国家重点实验室，河北 保定 071003
    2 北京智慧能源研究院，北京 102209

通讯作者:

谢庆（1979-），男（汉族），四川广元人，教授，博士，主要从事高电压与绝缘技术方面的研究。
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鹅膏菌科Amanitaceae 2 11 5.26 鹅膏菌属 Amanita 10 4.78
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