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Article(id=1251457069476430717, tenantId=1146029695717560320, journalId=1251194703438200922, issueId=1251457062706820082, articleNumber=null, orderNo=null, doi=10.14106/j.cnki.1001-2028.2025.0021, pmid=null, cstr=null, oa=null, hot=null, price=null, onlineType=0, articleFormat=0, articleType=null, articleTypeStr=null, receivedDate=1736611200000, receivedDateStr=2025-01-12, revisedDate=null, revisedDateStr=null, acceptedDate=null, acceptedDateStr=null, onlineDate=1776300216310, onlineDateStr=2026-04-16, pubDate=1759593600000, pubDateStr=2025-10-05, doiRegisterDate=null, doiRegisterDateStr=null, onlineIssueDate=1776300216310, onlineIssueDateStr=2026-04-16, onlineJustAcceptDate=null, onlineJustAcceptDateStr=null, onlineFirstDate=null, onlineFirstDateStr=null, sourceXml=null, magXml=null, createTime=1776300216310, creator=13041195026, updateTime=1776300216310, updator=13041195026, issue=Issue{id=1251457062706820082, tenantId=1146029695717560320, journalId=1251194703438200922, year='2025', volume='44', issue='10', pageStart='1119', pageEnd='1244', issueExtLink='null', onlineDate='null', pubDate='null', beforeIssueId=null, nextIssueId=null, price=null, status=1, issueComplete=1, articleOrder=1, issueType=1, specialIssue=null, createTime=1776300214696, creator=13041195026, updateTime=1776300327814, updator=13041195026, preIssue=null, nextIssue=null, ext={EN=IssueExt(id=1251457537212629591, tenantId=1146029695717560320, journalId=1251194703438200922, issueId=1251457062706820082, language=EN, specialIssueTitle=, coverIllustrator=null, specialIssueEditor=, specialIssueAbout=), CN=IssueExt(id=1251457537212629592, tenantId=1146029695717560320, journalId=1251194703438200922, issueId=1251457062706820082, language=CN, specialIssueTitle=, coverIllustrator=null, specialIssueEditor=, specialIssueAbout=)}, issueFiles=null}, startPage=1204, endPage=1210, ext={EN=ArticleExt(id=1251457069707117440, articleId=1251457069476430717, tenantId=1146029695717560320, journalId=1251194703438200922, language=EN, title=A high PSRR bandgap reference with piecewise curvature compensation, columnId=1251457065399563262, journalTitle=Electronic Components and Materials, columnName=Research & Development, runingTitle=null, highlight=null, articleAbstract=

To address the limitations of conventional opamp-free bandgap reference architectures—specifically their high temperature coefficient and insufficient power supply rejection ratio（PSRR）performance，which fail to meet high-precision application requirements—a high-PSRR bandgap reference circuit with segmented curvature compensation was designed. The proposed bandgap reference circuit adopts a voltage self-regulation structure，which suppresses power supply ripple in the low-frequency range through a negative feedback loop and enhances the anti-interference capability of the output voltage. Furthermore，a PTAT2（proportional to absolute temperature squared）compensation circuit was integrated to generate a compensation current，enabling segmented curvature compensation and thus realizing a significant reduction in the temperature coefficient. The proposed bandgap reference circuit was designed based on the SMIC 0.18 μm CMOS process. Simulation results indicate that，at an operating voltage of 3.3V，the bandgap reference output voltage is 1.197V；over the temperature range of-45 ℃ to 125 ℃，the temperature coefficient is 5.38×10-6/℃. The PSRR of this bandgap reference at low frequencies reaches-103dB，and the circuit has a quiescent current of 14.8 μA.

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针对传统无运放带隙基准结构温度系数较高、电源抑制比（PSRR）性能较差，难以满足高精度应用需求的问题，设计了一种具有分段曲率补偿的高PSRR带隙基准电路。该电路采用电压自调节电路结构，通过负反馈环路抑制低频范围内电源纹波，增强输出电压的抗干扰能力。同时为了降低带隙基准的温漂系数，引入PTAT2电路产生补偿电流，对电路进行分段曲率补偿。提出的带隙基准电路采用SMIC 0.18 μm工艺进行设计，结果表明，在3.3V工作电压下，带隙基准输出电压为1.197V；在-45～125 ℃温度范围内，温度系数为5.38×10-6/℃，低频下带隙基准源的PSRR为-103dB，电路的静态电流为14.8 μA。

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通信作者：武华，副教授，博士，主要研究方向为模拟集成电路设计。E-mail:
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Comparison of performance parameters between the bandgap referencecircuit in this paper and other literatures

, figureFileSmall=null, figureFileBig=null, tableContent=
参数文献[12]文献[13]文献[14]文献[15]本文
工艺（μm）0.180.180.180.180.18
电源电压（V）1.83.33.353.3
基准电压（V）0.81.2471.21.1921.197
温度范围（℃）-40～125-55～125-40～150-40～150-40～125
温度系数（10-6/℃）343.0295～154.845.38
电源抑制比（dB@DC）-75-98.36-80-78-103
静态电流（μA）512.43150—14.8
), ArticleFig(id=1251457086727602608, tenantId=1146029695717560320, journalId=1251194703438200922, articleId=1251457069476430717, language=CN, label=表1, caption=

本文带隙基准与其他文献的性能参数对比

, figureFileSmall=null, figureFileBig=null, tableContent=
参数文献[12]文献[13]文献[14]文献[15]本文
工艺（μm）0.180.180.180.180.18
电源电压（V）1.83.33.353.3
基准电压（V）0.81.2471.21.1921.197
温度范围（℃）-40～125-55～125-40～150-40～150-40～125
温度系数（10-6/℃）343.0295～154.845.38
电源抑制比（dB@DC）-75-98.36-80-78-103
静态电流（μA）512.43150—14.8
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一种带分段曲率补偿的高PSRR带隙基准
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朱春晓 1, 2 , 武华 1 , 周雨函 1 , 程家伟 1 , 曹先国 2
电子元件与材料 | 研究与试制 2025,44(10): 1204-1210
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电子元件与材料 | 研究与试制 2025, 44(10): 1204-1210
一种带分段曲率补偿的高PSRR带隙基准
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朱春晓1, 2, 武华1 , 周雨函1, 程家伟1, 曹先国2
作者信息
  • 1赣南师范大学 物理与电子信息学院，江西 赣州 341000
  • 2四川芯盛芯国科技有限公司，四川 成都 610000

通讯作者:

通信作者：武华，副教授，博士，主要研究方向为模拟集成电路设计。E-mail:
A high PSRR bandgap reference with piecewise curvature compensation
Chunxiao ZHU1, 2, Hua WU1 , Yuhan ZHOU1, Jiawei CHENG1, Xianguo CAO2
Affiliations
  • 1College of Physics and Electronic Information, Gannan Normal University, Ganzhou 341000, Jiangxi Province, China
  • 2Sichuan Xinsheng Xinguo Technology Co., Ltd., Chengdu 610000, China
出版时间: 2025-10-05 doi: 10.14106/j.cnki.1001-2028.2025.0021
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摘要
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针对传统无运放带隙基准结构温度系数较高、电源抑制比（PSRR）性能较差，难以满足高精度应用需求的问题，设计了一种具有分段曲率补偿的高PSRR带隙基准电路。该电路采用电压自调节电路结构，通过负反馈环路抑制低频范围内电源纹波，增强输出电压的抗干扰能力。同时为了降低带隙基准的温漂系数，引入PTAT2电路产生补偿电流，对电路进行分段曲率补偿。提出的带隙基准电路采用SMIC 0.18 μm工艺进行设计，结果表明，在3.3V工作电压下，带隙基准输出电压为1.197V；在-45～125 ℃温度范围内，温度系数为5.38×10-6/℃，低频下带隙基准源的PSRR为-103dB，电路的静态电流为14.8 μA。

带隙基准  /  电压自调节  /  分段曲率补偿  /  电源抑制比

To address the limitations of conventional opamp-free bandgap reference architectures—specifically their high temperature coefficient and insufficient power supply rejection ratio（PSRR）performance，which fail to meet high-precision application requirements—a high-PSRR bandgap reference circuit with segmented curvature compensation was designed. The proposed bandgap reference circuit adopts a voltage self-regulation structure，which suppresses power supply ripple in the low-frequency range through a negative feedback loop and enhances the anti-interference capability of the output voltage. Furthermore，a PTAT2（proportional to absolute temperature squared）compensation circuit was integrated to generate a compensation current，enabling segmented curvature compensation and thus realizing a significant reduction in the temperature coefficient. The proposed bandgap reference circuit was designed based on the SMIC 0.18 μm CMOS process. Simulation results indicate that，at an operating voltage of 3.3V，the bandgap reference output voltage is 1.197V；over the temperature range of-45 ℃ to 125 ℃，the temperature coefficient is 5.38×10-6/℃. The PSRR of this bandgap reference at low frequencies reaches-103dB，and the circuit has a quiescent current of 14.8 μA.

bandgap reference  /  voltage self-regulation  /  piecewise curvature compensation  /  power supply rejection ratio
朱春晓, 武华, 周雨函, 程家伟, 曹先国. 一种带分段曲率补偿的高PSRR带隙基准. 电子元件与材料, 2025 , 44 (10) : 1204 -1210 . DOI: 10.14106/j.cnki.1001-2028.2025.0021
Chunxiao ZHU, Hua WU, Yuhan ZHOU, Jiawei CHENG, Xianguo CAO. A high PSRR bandgap reference with piecewise curvature compensation[J]. Electronic Components and Materials, 2025 , 44 (10) : 1204 -1210 . DOI: 10.14106/j.cnki.1001-2028.2025.0021
正文
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带隙基准（BGR）电路作为现代集成电路系统中必不可少的基本电路模块，其性能对整个信号处理系统有着至关重要的影响[1-4]。随着电子设备朝着小型化、高性能化方向不断的发展，对带隙基准的性能提出了更为严苛的要求，尤其是电源抑制比（PSRR）和温度系数（TC）这两个衡量其性能的重要指标。高PSRR的带隙基准能够有效地降低电源噪声对基准电压的干扰，从而保障电路输出的稳定性和准确性。低温度系数的BGR则能确保系统在全温度范围内正常工作，可以减小因温度波动导致的性能退化。
为了提高BGR的性能指标，Chen等[5]提出了一种共享失调电压补偿方案，在-40～150 ℃温度范围内，放大器引入的模拟输出误差控制在5σ失调范围内，得到了5.78×10-6/℃的温度系数和-82dB@10kHz的电源抑制比。但由于引入了多个放大器，导致了电路整体的功耗和噪声较大。为了降低功耗，Duan等[6]通过工作在亚阈值区MOS管的温度特性对带隙基准电路进行了温度补偿，但由于工作在亚阈值区晶体管的工作点难以控制，在实际工艺条件下，该补偿方案的可行性会受到严重制约。Li等[7]则通过高阶曲率补偿来降低带隙基准的温度系数，在低压条件下实现了1.64×10-6/℃的低温度系数，但其PSRR仅为-50dB@1kHz。Xie等[8]基于改进的翻转电压跟随器（FVF），提出了一种反馈深度增强技术，使BGR的低频PSRR高达-184dB，但其最佳温度系数为22.04×10-6/℃。由此可见，国内外学者对BGR性能提升的研究还存在不足之处，开展对高PSRR、低温度系数的带隙基准电路结构的进一步研究仍具有重要的现实意义。
针对上述问题，本文提出了一种具有分段补偿的高PSRR带隙基准电压电路。该BGR采用电压自调节电路结构，通过引入负反馈环路来提高低频下的PSRR性能。利用PTAT2电路在不同温度段产生相应的补偿电流对电路进行分段曲率补偿，有效地降低了基准的温度系数，提高了电路的温度稳定性。
1　传统带隙基准
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传统的电压模带隙基准结构如图1所示。该结构利用M1～M4构成的电流镜及负反馈环路迫使A、B两点电压相等。将Q1和Q2基极-发射极电压差值ΔVBE作用于电阻R1上产生的正温度系数电流（PTAT），与负温度系数电压VEB进行加权求和，得到了一个与温度无关的基准电压。
电流IPTAT和输出电压Vref的关系可表示为：
式中：VEB3为晶体管Q3的发射结电压；VT为热电压，常温下约为26mV；N为Q1与Q2发射结面积之比。由式（1）可得，图1所示电路结构的PSRR表达式[9]为：
式中：νref为Vref的扰动量；νdd为VDD的扰动量；rex为Qx（x=1，2，3）的集电极电阻。为了得到图1所示传统BGR电路中iPTAT与νdd的关系，建立了如图2所示传统BGR电路的小信号模型。
根据基尔霍夫电流定律可得以下等式：
式中：gm3 =gm4；iPTAT =GM1νN；GM1表示从M1看进去的等效跨导，可由式（4）表示：
联立式（3）、（4）可得iPTAT与νdd的关系：
式中：RA =R1+re1；RB =1/gm2+re2。
2　电路设计与实现
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本文提出的带隙基准电路如图3所示，电路主要由四个模块构成，分别为启动电路、电压自调节电路、带隙核心电路、PTAT2电路。
2.1　曲率补偿电路
正向偏置的PNP三极管VEB与温度的关系[10]可表示为：
式中：（T/Tr）[VEB（Tr）-VG0]为VEB与温度相关的线性项，（n-δ）VTln（T/Tr）为VEB与温度相关的非线性项；VG0是0K时硅的带隙电压；n是一个与温度无关、与工艺有关的常数，约为4；δ是集电极电流的温度依赖性因子，如果三极管中的电流为PTAT，则等于1，如果电流与温度无关，则等于0。图1所示的传统BGR电路通过选择合适的R1和R2的电阻值来抵消式（6）的线性项，实现一阶温度补偿。但这种方式仅补偿了线性项，为了进一步降低温度系数，提升电路性能，还需对式（6）中的非线性项进行补偿。
本文在传统无运放的带隙基准电路结构的基础上增加了PTAT2电路，以实现二阶曲率补偿。图3中，PTAT2电路由MP12～MP14、MN3和R3组成。由PTAT2电路产生电流，补偿式（7）中的非线性项。与IPTAT电流进行叠加后，经过电阻R2转换为输出电压Vref。电流随温度变化的曲线如图4所示，其输出表达式可表示为：
式中：I0是与MN3的宽长比（W/L）MN3有关的常数；ξ是非理想常数；VT是热电压；KN3 =μnCox（W/L）MN3。
当T＜T1时，MN3关断；当T1＜T＜T2时，MN3工作在亚阈值区；当T＞T2时，MN3工作在饱和区。T1取值范围为0～15 ℃，T2取值范围为75～95 ℃。为了减少电阻R3的PVT特性对分段温度补偿的影响，（nA级别）的大小应与IPTAT（μA级别）相差几个数量级。
2.2　PSRR增强机制
如图3所示，本文所采用的电压自调节结构由MOS管MP5～MP10、MN4～MN8和电容C组成。其中，由MP6、MN5和MN6组成的低阻抗支路（LIB）是该电路结构的核心，主要用于检测VREG的变化。LIB对地的等效阻抗越低，抑制电源噪声的效果就越好。电容C用于降低主极点频率，提高电路的稳定性。
当电源电压VDD波动时，因为IA是PTAT电流源的复制电流，MP7和MP8的栅源电压VGS保持不变[11]，因此，MP7中的小信号电流变化id可表示为：
根据基尔霍夫电流定律可得：
式中：ib、ie、ip分别代表流过MP9、MP6和MP5支路的小信号电流，它们均为PTAT电流源的复制电流，不受νdd的影响；icore代表带隙基准电路所需要的电流，该电流与绝对温度成正比，当VDD出现波动时，几乎没有变化。与此同时，在如图3所示的Loop中，VREG通过负反馈环路进行调节，MP6、MN5将VREG的波动量放大后，在MN6中形成反馈电流，转换成IC的变化量ic，即：
式中：req表示LIB对地的等效阻抗。因此，电源电压波动产生的电流id全部流过MN6。联立式（8）和式（10），可得：
图5所示为LIB的小信号等效模型，根据基尔霍夫电流定律可得ix :
联立式（12）和式（13），可得req的表达式：
由于所有MOS管都工作在饱和区，所以rds，P7远远大于req。由式（11）可知νreg远小于νdd，通过调整MOS管的宽长比，可以进一步提升电路的PSRR。联立（11）、（14）两式，可以得到νreg和νdd的关系式为：
将式（5）中的νdd替换成νreg，再联立式（2）可进一步推得νref和νreg的关系式：
继续联立（15）、（16）两式，可得本文所提出的电路结构的PSRR表达式：
3　仿真验证和结果分析
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基于SMIC 0.18 μm工艺，使用Cadence Spectre对所设计的带隙基准电路进行了仿真验证，结果如图6～10所示。
在3.3V的工作电压下，设置温度范围为-40～125 ℃，对带隙基准电路进行了温度特性仿真。得到了未添加PTAT2电路时该电路结构的温度特性曲线如图6所示，添加了PTAT2电路后该电路结构在不同工艺角下的温度特性曲线如图7所示。本文所提出的BGR经过温度补偿后，有两个近似于零温度系数温度点，通过对比可以看出，具有补偿电流的带隙基准电路的温度系数显著减小。经过计算，在tt工艺角下有最好的温度系数，温漂系数为5.38×10-6/℃。在fnsp工艺角下温度系数最差，温漂系数为21.89×10-6/℃，主要归因于工艺的偏差带来的多晶硅电阻阻值变化，可通过增加修调电路进一步优化电路性能。
考虑到带隙基准电路的工作环境和性能要求，使用蒙特卡洛仿真来评估由于失配和工艺变化产生的对电路稳定性的影响。图8所示为取样500个点，输出电压的蒙特卡洛仿真结果。可以看到本文所提出的带隙基准Vref的平均值约为1.197V，标准差为4.411mV。输出的参考电压对工艺变化的敏感度较低。
图9所示为启动电路的瞬态仿真曲线。可以看出，电源电压在1μs后上升到3.3V，启动电路在5μs时完成启动，当带隙基准源的输出稳定后，启动电路关闭。
图10是Vref在不同工艺角下的电源抑制比（PSRR）仿真曲线。在典型工艺角下，低频时电路的PSRR为-103dB，1MHz时电路的PSRR仍有-35.8dB。可以看出，本文所设计的电路在各工艺角下的电源抑制比均表现良好。
表1为本文所提出的带隙基准电路结构的性能，并与其他文献电路结构的相关性能进行对比。可以看出，本文所提出的电路在保证了具有相对较低功耗的同时，还有高PSRR和低温度系数。
4　结论
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本文基于SMIC 0.18 μm CMOS工艺设计了一种低温度系数和高PSRR的带隙基准电压源电路。在传统无运放带隙基准电路结构的基础上，采用电压自调节电路提升电路的PSRR性能。此外，还使用了PTAT2电路产生补偿电流，对电路进行温度分段补偿，极大地提高了基准电压源的精度。仿真结果表明，该设计在宽温度范围内具有较好的性能，在3.3V电源电压下，输出的基准电压约为1.197V，在tt工艺角下，温度系数在-40～125 ℃范围内为5.38×10-6/℃，PSRR为-103dB@DC。所提出的电路结构提升了带隙基准的精度和温度稳定性，能够很好地应用于高精度的场合。未来可通过增加修调电路降低工艺的偏差带来的影响，进一步优化电路性能。
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2025年第44卷第10期
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doi: 10.14106/j.cnki.1001-2028.2025.0021
  • 接收时间：2025-01-12
  • 首发时间：2026-04-16
  • 出版时间：2025-10-05
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  • 收稿日期：2025-01-12
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    1赣南师范大学 物理与电子信息学院，江西 赣州 341000
    2四川芯盛芯国科技有限公司，四川 成都 610000

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通信作者：武华，副教授，博士，主要研究方向为模拟集成电路设计。E-mail:
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