Article(id=1322532027761545546, tenantId=1146029695717560320, journalId=1146031654075715584, issueId=1322531779840426416, articleNumber=null, orderNo=null, doi=10.13234/j.issn.2095-2805.2026.7.1, pmid=null, cstr=null, oa=null, hot=null, price=null, onlineType=0, articleFormat=0, articleType=null, articleTypeStr=null, receivedDate=1714320000000, receivedDateStr=2024-04-29, revisedDate=1730649600000, revisedDateStr=2024-11-04, acceptedDate=1732464000000, acceptedDateStr=2024-11-25, onlineDate=1793245806875, onlineDateStr=2026-10-29, pubDate=1785340800000, pubDateStr=2026-07-30, doiRegisterDate=null, doiRegisterDateStr=null, onlineIssueDate=1793245806875, onlineIssueDateStr=2026-10-29, onlineJustAcceptDate=null, onlineJustAcceptDateStr=null, onlineFirstDate=null, onlineFirstDateStr=null, sourceXml=null, magXml=null, createTime=1793245806875, creator=13701087609, updateTime=1793245806875, updator=13701087609, issue=Issue{id=1322531779840426416, tenantId=1146029695717560320, journalId=1146031654075715584, year='2026', volume='24', issue='7', pageStart='1', pageEnd='368', issueExtLink='null', onlineDate='null', pubDate='1785340800000', pubDateStr='2026-07-30', beforeIssueId=null, nextIssueId=null, price=null, status=1, issueComplete=1, articleOrder=1, issueType=-1, specialIssue=null, createTime=1793245747766, creator='13701087609', updateTime=1793245747766, updator='13701087609', preIssue=null, nextIssue=null, articleTotal=null, ext=null, issueFiles=null, downloadFileDto=null}, startPage=1, endPage=7, ext={EN=ArticleExt(id=1322532028180975947, articleId=1322532027761545546, tenantId=1146029695717560320, journalId=1146031654075715584, language=EN, title=A New Structural Design of UMOSFET with PN-Bottom, columnId=1321491639659516540, journalTitle=Journal of Power Supply, columnName=Power Semiconductor Devices and Drive Circuits, runingTitle=null, highlight=null, articleAbstract=

Due to the trade-off relationship between breakdown voltage (BV) and specific on-resistance R_on,sp, to minimize the decrease in breakdown voltage while reducing on-resistance, an improved U-trench metal-oxide-semiconductor field-effect transistor (UMOSFET) structure with PN-Bottom is proposed. First, on the basis of traditional 100 V U-trench metal-oxide-semiconductor (UMOS) devices, deep trench etching technology is adopted to introduce a PN-Bottom wrapping region at the bottom of the trench, which wraps the P-type region inside the N-type region. Then, the new structural parameters and fabrication process of the device are introduced. Next, using the TCAD simulation tool, a detailed discussion was conducted on the doping concentration, width, and depth of the N-Bottom and P-Bottom encapsulation regions, and their effects on the breakdown voltage and specific on-resistance of the device were studied. Finally, the simulation results show that under the same conditions, an optimized design with BV of 110 V and R_on,sp of 1.15 mΩ·cm² was obtained.

, authors=Chunhui PEI, Quanyuan FENG, authorsList=Chunhui PEI, Quanyuan FENG, authorCompany=null, correspAuthors=Quanyuan FENG, authorNote=null, correspAuthorsNote=null, copyrightStatement=null, copyrightOwner=null, extLink=null, articleAbsUrl=null, sourceXml=null, magXml=null, pdfUrl=null, pdf=null, pdfFileSize=null, pdfExtLink=null, richHtmlUrl=null, mobilePdfUrl=null, reviewReport=null, pdfFirstPage=null, abstractGraph=null, abstractGraphContent=null, abstractVideo=null, citation=null, cebUrl=null, magXmlContent=null, mapNumber=null, fund=null), CN=ArticleExt(id=1322532029443461455, articleId=1322532027761545546, tenantId=1146029695717560320, journalId=1146031654075715584, language=CN, title=一种具有PN-Bottom的UMOSFET新结构设计, columnId=1321491641425318526, journalTitle=电源学报, columnName=功率半导体器件与驱动, runingTitle=null, highlight=null, articleAbstract=

由于击穿电压BV（breakdown voltage）和特征导通电阻R_on,sp之间存在折中关系，为了在减小导通电阻的同时尽可能抑制击穿电压的下降，提出了一种改进的具有PN-Bottom的U型金属氧化物半导体场效应晶体管UMOSFET（U-trench metal-oxide-semiconductor field-effect transistor）结构。首先在传统100 V U型金属氧化物半导体UMOS（U-trench metal-oxide-semiconductor）器件的基础上，采用深沟槽刻蚀技术，在沟槽底部引入了一个PN型包裹区PN-Bottom，N型区将P型区包裹在内；然后介绍了器件的新结构参数和制备工艺流程；接着借助TCAD仿真工具，对N型包裹区和P型包裹区的掺杂浓度、宽度和深度进行详细讨论，研究了其对器件击穿电压和特征导通电阻的影响；最后在控制其他参数不变的条件下，实现了击穿电压为110 V、特征导通电阻为1.115 mΩ·cm²的优化设计。

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裴春荟（2000—　），女，硕士。研究方向：功率器件。E-mail：1468803401@qq.com。

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裴春荟（2000—　），女，硕士。研究方向：功率器件。E-mail：1468803401@qq.com。

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